131,640 research outputs found
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
No full textIn spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliabilit
EDACs and test integration strategies for NAND flash memories
No full textMission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device is always needed in all mission-critical applications: NAND flash-memories could be used for this goal. Error Detection And Correction (EDAC) techniques are needed to improve dependability of flash-memory devices. However also testing strategies need to be explored in order to provide highly dependable systems. Integrating these two main aspects results in providing a fault-tolerant mass-memory device, but no systematic approach has so far been proposed to consider them as a whole. As a consequence a novel strategy integrating a particular code-based design environment with newly selected testing strategies is presented in this pape
PLA Design in NAND Structure
No full textA NAND (serial gating) structure PLA of the MOS poly-silicon gate process has been developed for high density and medium fast speed VLSI application. Dynamic clocking is used for minimum power dissipation and
elimination of the ratio problem associated with static NAND gate. Ion-implantation for memory cell programming and the elimination of contact in the memory area drastically reduces the cell size, and reliability is improved .
A simple but effective self-timed clocking scheme is employed for better operating margins against process variations; the overhead chip area for the
clock generation is sufficiently small. The advantages of allowing metal signal and power lines to cross the PLA memory area is discussed. Some measured data
from a 3.5μm NMOS Si-gate process with regard to gate height and transistor sizes are also described
Improving Reliability and Performance of NAND Flash Based Storage System
No full textHigh seek and rotation overhead of magnetic hard disk drive (HDD) motivates development of storage devices, which can offer good random performance. As an alternative technology, NAND flash memory demonstrates low power consumption, microsecond-order access latency and good scalability. Thanks to these advantages, NAND flash based solid state disks (SSD) show many promising applications in enterprise servers. With multi-level cell (MLC) technique, the per-bit fabrication cost is reduced and low production cost enables NAND flash memory to extend its application to the consumer electronics.
Despite these advantages, limited memory endurance, long data protection latency and write amplification continue to be the major challenges in the designs of NAND flash storage systems. The limited memory endurance and long data protection latency issue derive from memory bit errors. High bit error rate (BER) severely impairs data integrity and reduces memory durance. The limited endurance is a major obstacle to apply NAND flash memory to the application with high reliability requirement. To protect data integrity, hard-decision error correction codes (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) are employed. However, the hardware cost becomes prohibitively with the increase of BER when the BCH ECC is employed to extend system lifetime. To extend system lifespan without high hardware cost, we has proposed data pattern aware (DPA) error prevention system design. DPA realizes BER reduction by minimizing the occurrence of data patterns vulnerable to high BER with simple linear feedback shift register circuits. Experimental results show that DPA can increase the system lifetime by up to 4× with marginal hardware cost.
With the technology node scaling down to 2Xnm, BER increases up to 0.01. Hard-decision ECCs and DPA are no longer applicable to guarantee data integrity due to either prohibitively high hardware cost or high storage overhead. Soft-decision ECC, such as lowdensity parity check (LDPC) code, has been introduced to provide more powerful error correction capability. However, LDPC code demands extra memory sensing operations, directly leading to long read latency. To reduce LDPC code induced read latency without adverse impact on system reliability, we has proposed FlexLevel NAND flash storage system design. The FlexLevel design reduces BER by broadening the noise margin via threshold voltage (Vth) level reduction. Under relatively low BER, no extra sensing level is required and therefore read performance can be improved. To balance Vth level reduction induced capacity loss and the read speedup, the FlexLevel design identifies the data with high LDPC overhead and only performs Vth reduction to these data. Experimental results show that compared with the best existing works, the proposed design achieves up to 11% read speedup with negligible capacity loss.
Write amplification is a major cause to performance and endurance degradation of the NAND flash based storage system. In the object-based NAND flash device (ONFD), write amplification partially results from onode partial update and cascading update. Onode partial update only over-writes partial data of a NAND flash page and incurs unnecessary data migration of the un-updated data. Cascading update is update to object metadata in a cascading manner due to object data update or migration. Even through only several bytes in the object metadata are updated, one or more page has to be re-written, significantly degrading write performance. To minimize write operations incurred by onode partial update and cascading update, we has proposed a Data Migration Minimizing (DMM) device design. The DMM device incorporates 1) the multi-level garbage collection technique to minimize the unnecessary data migration of onode partial update and 2) the virtual B+ tree and diff cache to reduce the write operations incurred by cascading update. The experiment results demonstrate that the DMM device can offer up to 20% write reduction compared with the best state-of-art works
TCAD modeling of current transport and main reliability issues of polysilicon-channel 3-D NAND Flash strings
No full textDOTTORATOLa tecnologia NAND Flash rappresenta oggi una delle soluzioni leader per le memorie non volatili ad alte prestazioni. Il continuo sviluppo dei suoi processi di produzione ha portato la dimensione caratteristica della cella (F) a valori attuali intorno ai 15 nm. Sebbene la miniaturizzazione degli array abbia permesso di aumentare drasticamente la densità di memoria e la riduzione dei costi negli ultimi decenni, ha anche portato molti problemi di affidabilità che sono stati superati sviluppando strutture NAND Flash 3-D, impiegando la terza dimensione, rilassando così la miniaturizzazione della cella e impilando più strati in direzione verticale. Uno degli svantaggi di queste nuove strutture è dato dal fatto che il canale è policristallino a causa dei processi di produzione coinvolti. Questa è una delle principali fonti di problemi nelle stringhe NAND Flash 3-D a causa della presenza di bordi di grano con un'alta concentrazione di stati difettosi. In particolare, questo causa sia un aumento della resistività del canale della stringa sia fluttuazioni di tensione di soglia causate da eventi casuali di cattura/emissione in questi stati di trappola. Inoltre, la configurazione casuale dei profili dei grani porta problemi di variabilità che devono essere presi in considerazione per progettare correttamente il dispositivo. A causa della complessità di tali dispositivi e dei problemi di affidabilità che ne derivano, è necessario prestare attenzione per evitare problemi durante il funzionamento. In questo quadro, la presente tesi mira a descrivere i problemi di trasporto di carica e i principali problemi di affidabilità nelle stringhe NAND Flash 3-D a canale verticale attraverso la modellazione TCAD tenendo conto della natura policristallina del canale. In particolare, sono state effettuate simulazioni per confrontare i risultati provenienti da diversi modelli per descrivere il trasporto corrente nel canale del polisilicio. Successivamente, il modello TCAD è stato calibrato su dati sperimentali ed è stato utilizzato per analizzare statisticamente l'attivazione in temperatura della variabilità della tensione di soglia e le fluttuazioni del Random Telegraph Noise (RTN) provenienti dalla disomogeneità della configurazione dei grani.NAND Flash technology represents today one of the leading solutions for highly performing non-volatile memories. The continuous development of its manufacturing processes brought the characteristic cell feature size (F) to current values around 15 nm. Although the scaling of the arrays allowed to drastically increase storage density and the reduction of costs over the past few decades, it also brought many reliability issues which were overcame by developing 3-D NAND Flash structures, employing the third dimension, thus relaxing the scaling of the cell and stacking multiple layers in the vertical direction. One of the drawbacks coming with these new structures is given by the channel being polycrystalline, due to the involved manufacturing processes. This is one of the major source of issues in 3-D NAND Flash strings, due to the presence of grain boundaries with a high concentration of defect states. More specifically, this causes both an increase of the resistivity of the string channel and also threshold voltage fluctuations caused by random trapping/detrapping events at these trap states. Moreover, the random configuration of grain profiles causes variability issues that have to be taken into account to properly design the device. Due to the complexity of such devices and the involved reliability issues, care must be taken in order to avoid issues during operation. In this framework, this thesis aims to describe current transport and main reliability issues in vertical-channel 3-D NAND Flash strings by means of TCAD modeling, accounting for the polycrystalline nature of the channel. In particular, simulations were performed to compare the results coming from different models to describe current transport in the polysilicon channel. Then, the TCAD model was calibrated on experimental data and it was used to statistically analyze the temperature activation of threshold voltage variability and Random Telegraph Noise (RTN) fluctuations coming from the haphazardness of grain configuration.DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIAElectronics33SOTTOCORNOLA SPINELLI, ALESSANDROPERNICI, BARBAR
ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES
No full textEnclosed in this thesis work it can be found the results of a three years long research
activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of
the Università degli Studi di Ferrara. The topic of this work is concerned about the
electrical characterization, physics, modeling and reliability of innovative non-volatile
memories, addressing most of the proposed alternative to the floating-gate based
memories which currently are facing a technology dead end. Throughout the chapters of
this thesis it will be provided a detailed characterization of the envisioned replacements for
the common NOR and NAND Flash technologies into the near future embedded and
MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the
non-volatile memory technology with direct reference on nowadays Flash mainstream,
providing indications and comments on why the system designers should be forced to
change the approach to new memory concepts. In Chapter 2 it will be presented one of the
most studied post-floating gate memory technology for MPSoCs: the Phase Change
Memory. The results of an extensive electrical characterization performed on these
devices led to important discoveries such as the kinematics of the erase operation and
potential reliability threats in memory operations. A modeling framework has been
developed to support the experimental results and to validate them on projected scaled
technology. In Chapter 3 an embedded memory for automotive environment will be shown:
the SimpleEE p-channel memory. The characterization of this memory proven the
technology robustness providing at the same time new insights on the erratic bits
phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the
research studies performed on a memory device based on the Nano-MEMS concept. This
particular memory generation proves to be integrated in very harsh environment such as
military applications, geothermal and space avionics. A detailed study on the physical
principles underlying this memory will be presented. In Chapter 5 a successor of the
standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory
shares the same principles of the traditional floating gate technology except for the storage
medium which now has been substituted by a discrete nature storage (i.e. silicon nitride
traps). The conclusions and the results summary for each memory technology will be
provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently
started research activity on the high level reliability memory management exploiting the
results of the studies for Phase Change Memories
Figure 3.5: NAND gates: (a) 2-input NAND gate; (b) Truth table; (c) 3- and 4-input NAND gates.
No full textFigure 3.5: NAND gates: (a) 2-input NAND gate; (b) Truth table; (c) 3- and 4-input NAND gates. The animation shows all possible values of inputs to the 2-input NAND gate and the output each set of input values generates
Investigation of Trap Profiling after P/E Cycling Stress in 3-D NAND Memory
No full textMasterRecently, three-dimensional (3-D) NAND Flash Memory has been continuously scaled down to further increase its density and manufacturing cost. The band engineering layer (BE) in 3-D NAND was generally introduced to enhance program speed without degrading reliability. However, even NAND with BE layer has been still sufferred from the trap generation especially when program/erase (P/E) cycling was performed. Accurate method of extracting traps in BE layers have necessitated in order to understand trap generation and charge loss mechanism in scaled 3-D NAND devices. Here, we extracted trap profiling in BE layers of 3-D NAND flash after P/E cycling stress using trap spectroscopy by charge injection and sensing (TSCIS) method. The trap profiling of the tunneling layer was extracted and compared both from SS and GS before and after P/E cycling stress. The trap generation was more significant in SS. The average trap density was increased by 30 % at 2.6 nm from the poly-Si /tunneling layer interface, and by 28% at EC ET = 1.6 eV, respectively. In GS case, relatively small variaiton of trap density was oberved after the P/E stress. The trap profiling in 3-D NAND memory has successfully demonstrated. The trap profiling could be very useful to evaluate the robustness of bandgap engineerd dielectric layers in developing next flash devices with further scaling
Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping
No full textThe examination of the effect of retrograde channel doping on reliability and performance of 3-D junction-free NAND based flash memory is done for this paper. Specifically, we study the program characteristics, data retention capability junction-free NAND flash memory with half pitch range from 35 nm to 12 nm. Based on our analysis, we highlight that the retrograde channel doping approach can improve not only the SCEs but also the program speed and data control time for 3-D junction-free NAND flash memory, without varying the oxide stack in charge trap-based flash memory
Alternatieve kanaalmaterialen voor 3-D NAND geheugen
No full textNowadays consumer’ s electronic such as smart phones, tablet, laptops, GPS navigators, health care devices, music players and digital photo/video cameras, is an inextricable part of the modern society and represents one of the fastest growing markets on the earth; the steadily increasing demand for portable devices requiring data storage in huge volume, has triggered an exceptional growth of non-volatile memory market. Non-volatile memories can retain the stored information even when not powered, and there are various solutions available in the market to serve the need of different applications: hard drives, magnetic tapes, compact disks, NAND and NOR flash memories, etc. . Among them, the most popular for mass data storage application are hard drives and NAND flash. Hard drive disks (HDDs) use spinning magnetic platters paired with magnetic head to read and write data. On the other hand NAND flash is a semiconductor memory entirely implemented in solid state circuits, and it does not require moving parts. Even if the cost per bit is relatively higher than HDDs, NAND flash has becoming a new driving force in the semiconductor industry over the last decade, thanks to its proven scalability, low power consumption and robustness, fundamental for portable systems.
In order to overcome the scaling obstacle in conventional planar NAND Flash, 3D NAND memory technology, has been introduced for mass production for the first time in 2014. The third dimension is exploited by stacking NAND cells on top of each other’s, resulting not only in a significant bit‑density increase but also in a reduced cost-per-bit. The most industrial relevant channel material for 3D NANDs is polycrystalline silicon (poly-Si). However, the conduction in poly‑Si channel is dominated by the grain size distribution and hampered by scattering events at grain boundaries and charged defects. As a consequence, the drive current (ID) required for reading operations, is low, unstable, and decreases as the number of stacked cells increases, rendering poly‑Si unsustainable for long‑term scaling. This thesis is an effort to investigate alternative channel materials with higher electron mobility than poly-Si, as a possible solution to enable further scaling for future 3D NAND generations.status: Publishe
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