2,640 research outputs found
Towards minimum material trackers for high energy physics experiments at upgraded luminosities
No full textReducing material in silicon trackers is of major importance for a good detector performance overall, and poses a big challenge in the development of the detectors. To match the low material desirable for trackers in High Energy Physics experiments at upgraded luminosities, special techniques have to be developed to address the main sources of material, i.e. mechanical structure and services, and to prevent new significant contributions to the detector material coming for instance from larger Front-End chips. In this framework three methods are developed to reduce the material added by services and electronics: (1)serial powering, (2) light weight aluminum flex cables and Through Silicon Vias, and (3) thin Front-End chips. The methods are presented in this paper using the upgrades of the ATLAS pixel detector as an example of application. (C) 2010 Elsevier B.V. All rights reserved
The shunt-LDO regulator to power the upgraded ATLAS pixel detector
No full textThe shunt-LDO regulator is a new regulator concept which combines a shunt and a Low Drop-Out (LDO) regulator. Designed as an improved shunt regulator to match the needs of serially powered detector systems, it can also be used as a pure LDO regulator for general application in powering schemes requiring linear regulation. The flexibility of the design makes the shunt-LDO regulator a good candidate for use in the powering schemes envisaged for the upgrades of the ATLAS pixel detector. Two shunt-LDO regulators integrated in the prototype of the next ATLAS pixel front-end chip, the FE-I4A, are used to demonstrate the feasibility of the proposed powering solutions
Depleted Monolithic Pixels (DMAPS) in a 150 nm technology: lab and beam results
No full textThe fully depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a fully depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and high resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, were developed in a 150 nm process on a high resistive n-type wafer of 50 mu m thickness. The prototypes have 352 square pixels of 40 mu m pitch and small n-well charge collection node with very low capacitance (n(+) -implantation size: 5 mu m by 5 mu m) and about 150 transistors per pixel (CSA and discriminator plus a small digital part)
A serial powering pixel stave prototype for the ATLAS ITk upgrade
No full textOne of the main challenges for the ATLAS ITk Phase II Pixel upgrade is low-mass efficient power distribution for detector modules. This requires a powering scheme alternative to the parallel (direct) powering which is currently used. A serial powering scheme has been chosen as the baseline for the ITk pixel system. A serially powered pixel detector prototype has been built with all the components that are needed for current distribution, data transmission, bypassing and redundancy in order to prove the feasibility of implementing serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules have been made with the help of the USBpix3 readout system that has been developed in Bonn
A via last TSV process applied to ATLAS pixel detector modules: proof of principle demonstration
No full textVia last Through Silicon Vias (TSVs) can be exploited to build low material modules for the upgrades of the ATLAS pixel detector at the High Luminosity LHC. To prove this concept a via last TSV process is demonstrated on ATLAS pixel readout wafers. Demonstrator modules featuring 90 mu m thin readout chips with TSVs are operated using the connection from the back side of the chip. This paper illustrates the via formation process and the results from the characterization of modules with TSVs
Performance evaluation of a serially powered pixel detector prototype for the HL-LHC
No full textEfficient and low mass power distribution presents a challenge for vertex and tracking detectors at the HL-LHC. Different approaches have been considered to transmit power at low current and high voltage. This paper presents the serial powering scheme proposed as baseline for the ATLAS and CMS pixel detectors at the HL-LHC. A serially powered detector prototype with six pixel modules has been built, featuring all elements needed for current distribution, redundancy, data transmission, and sensor biasing. Results of the characterisation of the prototype in standard operating conditions as well as in more challenging scenarios including increased digital activity are presented
A serial powering scheme for the ATLAS pixel detector at sLHC
No full textPowering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. This paper will describe the serial powering scheme developed for the upgraded ATLAS pixel detector, with focus on the scheme architecture and on the main components involved: the Shunt-LDO regulator and the protection scheme. Issues connected to system aspects will be discussed, and the advantages in terms of material reduction provided by the proposed serial powering scheme will be presented
Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line
No full textPixel sensors using 8" CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 x 10(15) n(eq) cm(-2). The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation
Development of a versatile and modular test system for ATLAS hybrid pixel detectors
No full textThe insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USE-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed. (C) 2010 Elsevier B.V. All rights reserved
Neutron irradiation test of depleted CMOS pixel detector prototypes
No full textCharge collection properties of depleted CMOS pixel detector prototypes produced on p- type substrate of 2 k Omega cm initial resistivity (by LFoundry 150 nm process) were studied using EdgeTCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL- LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1 (.) 10(13) n/cm2 and 5 (.)10(13) n/cm2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1 (.) 10(15) n/cm2 is more than 50 mu m at 100V bias. This is sufficient to guarantee satisfactory signal/ noise performance on outer layers of pixel trackers in HL-LHC experiments
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