44 research outputs found
The effect of putrescine and difluoromethylornithine on cell division activity of wheat in different ploidy level
No full textEffects of exogenous putrescine (Put) and difluoromethylornithine (DFMO) on seed germination, root growth, mitotic activity and mitotic chromosome behavior were investigated in Triticum monococcum (2x), Triticum durum (4x) and Triticum aestivum (6x). Put and DFMO affected all three species, but diploid species was the most affected one in respect to seed germination, mitotic index and the occurrence of abnormality than the others. Reduction of the root growth in Put and DFMO treated samples was due to the reduction of mitotic activity in three species used in this research
A real-time, low latency, FPGA implementation of the 2-D discrete wavelet transformation for streaming image applications
No full textIn this paper, we present an architecture and a hardware implementation of the 2-D Discrete Wavelet Transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003
A real time, low latency, hardware implementation of the 2-D discrete wavelet transformation for streaming image applications
No full textIn this paper, we present a 2-D Discrete Wavelet Transformation (DWT) hardware for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003
Low-power Design of a Digital FM Demodulator based
No full textA digital FA4 receiver/demodulator system, utilizing the zero-cross detection technique [l]> is designed and implemented on a single IC. Zero-cross detection is performed at an IF frequency of 455 kHz. The system is simulated for BT=0.3 GMSK input with an input data rate of 8000 bps and displayed a better BER Performance than coherent detectors. The developed system is implemented in 0.5 pm triple-metal standard digital CMOS technology. Power dissipation of the resultant IC is less than its analog counterparts while the occupied silicon area is very small making it low cost. The FM receiver/demodulator IC is suitable to be used in low-power and low-cost mobile communication applications providing better BER performance than conventional systems. especially in noisy channels. 1
Design of a Fully-static Differential Low-Power CMOS Flip-flop
No full textA fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [I], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure showed to be consuming less power and occupying smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures. 1
Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS
No full textA 4-bit 64-chip Pseudo Noise (PN) coded Digital Matched Filter (DMF) is designed in 0.7um CMOS technology using Systolic Array (SA) architecture. Full-custom and full-static Cascode Voltage Switch Logic (CVSL) circuit techniques have been employed in the implementation of the basic building blocks (systoles) of the SA DMF. Significant reduction in number of transistors and power consumption have been achieved. The resultant IC is to be used at the receiver side of a wireless Direct Sequence Spread Spectrum (DSSS) communication system
Design of a fully-static differential low-power CMOS flip-flop
No full textA fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [1], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure showed to be consuming less power and occupying smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures
A low-power system-on-chip for telecommunications: single chip digital FM receiver/demodulator IP
No full text
