511 research outputs found
Interface Trap Density Metrology from Sub-Threshold Transport in Highly Scaled Undoped Si n-FinFETs
No full textChannel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight- Binding (TB) calculations, this technique can be used to understand the evolution of source-to- channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |∂Eb/∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage
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The Impact of Width Downscaling on the High-Frequency Characteristics of InGaAs Nanowire FETs
No full textThis work was supported in part by the "Center for the Semiconductor Technology Research" from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE), Taiwan; in part by the Ministry of Science and Technology, Taiwan, under Grant NSTC-110-2622-8-A49-008-SB, Grant NSTC-111-2622-8-A49-018-SB, and Grant NSTC-111-2634-F-A49-008; and in part by the National Chung-Shan Institute of Science and Technology under Grant NCSIST-404-V407(111)
Impact of III-N buffer layers on RF losses and harmonic distortion of GaN-on-Si Substrates
No full textThe reduction of substrate RF losses and nonlinearities is key to enable high-performance GaN-on-Si HEMT based RF front-end modules. In this paper, the impact of the epitaxial III-N buffer layers on substrate RF losses and harmonic distortion is studied experimentally using coplanar waveguide (CPW) structures. In contrast to a SiO2/Si stack, a strong hysteresis in the RF losses (quantified using effective resistivity (rho_eff) of the HEMT stack is observed when the chuck DC bias is swept. A comparative analysis of various material stacks suggests that the hysteresis originates from the large time constants (much larger than 1 s) associated with the traps in the III-N layers. Harmonic distortion, on the other hand, shows much weaker hysteresis effect than reff during chuck bias sweep
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No full textFront.: Adri. Collaert excud.F. 2R8 : Dit leven is wt de Fransoysche Cronijcke der Minderbroeders ghenomen, ghemaeckt door [...] P. Marcus van Lisbone [...] ghetraslateert door B. Corn. Thielmans [...]Vingerafdruk: 162308 - # b1 2R2 oor : # b2 2R5 ndeBib. catholica Neerlandica impressa ; 7221Europeana-GoogleBook
Dislocations behavior in highly mismatched III-Sb growth and their impact on the fabrication of top-down n plus InAs/p plus GaSb nanowire tunneling devices
No full text© 2018 Author(s). We study in this work the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates. A careful investigation on the highly mismatched GaSb/GaAs growth is first conducted by means of Reflection High-Energy Electron Diffraction (RHEED), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD) analyses. These results are expected to pave the way to methods for III-Sb buffer layer's integration with low threading dislocation (TD) densities. A comparison between AFM, XRD, defect revealing by chemical etching and transmission electron microscopy (TEM) is then presented to calculate the precise TD density and its influence on the device structure. In the last part, we report on first operating sub-30 nm III-V vertical NW tunneling devices on (001) commercial GaAs substrates.status: Publishe
Low-frequency-noise investigation of n-channel bulk FinFETs developed for one-transistor memory cells
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