1,720,975 research outputs found
Analysis of double-gate MOS structures by solving Poisson and Schroedinger equations with open boundaries
No full text
Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs
No full textState-of-the-art device simulation is applied to the
analysis of possible scaling strategies for the future CMOS technology,
adopting the ultrathin silicon body (UTB) double-gate
(DG) MOSFET and considering the main figures of merit (FOM)
for the high-performance N-MOS transistor. The results of our
analysis confirm the potentials of UTB-DG MOSFETs. In particular,
the possibility to control the short-channel effects by
thinning the silicon layer is fully exploited allowing to adopt
almost undoped silicon channel, leading to reduced transversal
field. As a consequence, the impact of surface roughness at the
Si-oxide interface and the gate tunneling leakage current are
substantially reduced compared to the case of highly doped bulk
MOSFETs. According to our results, thanks to the suppression of
gate leakage current, scaling of the UTB-DG MOSFET down to
the 32 nm technology node appears possible adopting SiO2-based
gate dielectrics. In spite of the improved mobility at given inversion
charge density, the simulated on-currents are substantially lower
than those required by the 2005 ITRS for the 45 and 32 nm nodes. Nonetheless, thanks to relaxed scaling of the oxide thickness,
hence to reduced gate capacitance, the requirements in terms of
intrinsic delay and power-delay product can be satisfied. The issue
of variability is analyzed by evaluating the dependence of the key
FOM on the variation of critical dimensions such as the thickness
of the gate oxide and of the silicon layer
Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-Signal and RF applications
No full textIn this work, a Monte-Carlo simulator including the most relevant scattering mechanisms and quantum corrections to the potential, already extensively applied to the DC analysis of ultra-short devices and upgraded in order to allow RF device analysis, is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET.
Original contributions consist in the analysis of the signal-delay build-up along the channel and investigation of the scaling properties of the parameters of the AC equivalent circuit, transition frequency FT and 3dB bandwidth of the voltage gain in common-source configuration.
The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB Double-Gate (DG) MOSFETs
Stability of Self-Consistent Monte Carlo Simulations: Effects of the Grid Size and of the Coupling Scheme
No full textn this paper, the authors show that the grid spacing affects the stability of self-consistent Monte Carlo device simulations. An analytical model is derived to describe this effect. Guidelines for the choice of the grid size are provided, showing that, when the linear Poisson scheme is used, source/drain extensions with doping level as high as 1020 cm-3 require grid spacing lower than 1 nm in order to have stable simulations. On the other hand, the nonlinear coupling scheme does not impose any constraint, provided that the time between two solutions of the Poisson equation is so long that each solution can be considered as a stationary solution of the Boltzmann transport equation
Scaling the High-Performance Double-Gate SOI MOSFET down to the 32 nm Technology Node with SiO2-based Gate Stacks
No full textWe apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I
Stability of Self-Consistent Monte-Carlo Simulations: Revised Analysis of Linear and Non-Linear Poisson Schemes
No full textMonte-Carlo Analysis of Signal Propagation Delay and AC Performance of Decananometric Bulk and Double-Gate MOSFETs
No full textA time-dependent simulation procedure has been implemented in a state of the art Monte Carlo device simulator that includes quantum corrections and applied to the evaluation of the RF performance of bulk and ultra-thin-body double-gate (UTB-DG) MOSFETs with LG = 25 nm.
The analysis focuses on the evaluation of the signal delay along the channel and of the admittance matrix at the device terminals.
The performance of the bulk and UTB-DG MOSFETs are compared; the latter provides a significantly larger transition frequency (FT), due to the larger trans-conductance and much lower total drain capacitance, thanks to suppressed junction capacitance
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