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MAGNETO-ELECTRIC APPROXIMATE COMPUTATIONAL FRAMEWORK FOR BAYESIAN INFERENCE
Get PDFProbabilistic graphical models like Bayesian Networks (BNs) are powerful artificial-intelligence formalisms, with similarities to cognition and higher order reasoning in the human brain. These models have been, to great success, applied to several challenging real-world applications. Use of these formalisms to a greater set of applications is impeded by the limitations of the currently used software-based implementations. New emerging-technology based circuit paradigms which leverage physical equivalence, i.e., operating directly on probabilities vs. introducing layers of abstraction, promise orders of magnitude increase in performance and efficiency of BN implementations, enabling networks with millions of random variables. While majority of applications with small network size (100s of nodes) require only single digit precision for accurate results, applications with larger size (1000s to millions of nodes) require higher precision computation. We introduce a new BN integrated circuit fabric based on mixed-signal magneto-electric circuits which perform probabilistic computations based on the principle of approximate computation. Precision scaling in this fabric is logarithmic in area vs. linear in prior directions. Results show 33x area benefit for a 0.001 precision compared to prior direction, while maintaining three orders of magnitude performance benefits vs. 100-core processor implementations.Master of Science (M.S.
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Parameter Variation Sensing and Estimation in Nanoscale Fabrics
No full textParameter variations introduced by manufacturing imprecision are becoming more influential on circuit performance. This is especially the case in emerging nanoscale fabrics due to unconventional manufacturing steps (e.g., nano-imprint) and aggressive scaling. These parameter variations can lead to performance deterioration and consequently yield loss. Parameter variations are typically addressed pre-fabrication with circuit design targeting worst-case timing scenarios. However, this approach is pessimistic and much of performance benefits can be lost. By contrast, if parameter variations can be estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance. To estimate parameter variations during run-time, on-chip variation sensors are gaining in importance because of their easy implementation. In this thesis, we propose novel on-chip variation sensors to estimate variations in physical parameters for emerging nanoscale fabrics. Based on the characteristics of systematic and random variations, two separate sensors are designed to estimate the extent of systematic variations and the statistical distribution of random variations from measured fall and rise times in the sensors respectively. The proposed sensor designs are evaluated through HSPICE Monte Carlo simulations with known variation cases injected. Simulation results show that the estimation error of the systematic-variation sensor is less than 1.2% for all simulated cases; and for the random-variation sensor, the worst-case estimation error is 12.7% and the average estimation error is 8% for all simulations. In addition, to address the placement of on-chip sensors, we calculate sensor area and the effective range of systematic-variation sensor. Then using a processor designed in nanoscale fabrics as a target, an example for sensor placement is introduced. Based on the sensor placement, external noises that may affect the measured fall and rise times of outputs are identified. Through careful analysis, we find that these noises do not deteriorate the accuracy of the systematic-variation sensor, but affect the accuracy of the random-variation sensor. We believe that the proposed on-chip variation sensors in conjunction with post-fabrication compensation techniques would be able to improve system-level performance in nanoscale fabrics, which may be an efficient alternative to making worst-case assumptions on parameter variations in nanoscale designs.Master of Science in Electrical and Computer Engineering (MSECE
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A Theoretical Approach to Fault Analysis and Mitigation in Nanoscale Fabrics
Get PDFHigh defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuit and logic styles. Thus, theoretical fault models for nanosystems are necessary to extract detailed characteristics of fault generation and propagation. Using the intuition garnered from the theoretical analysis, modular and structural redundancy schemes can be specifically tailored to the intricacies of the fabric in order to achieve higher reliability of output signals. In this thesis, we develop a detailed analytical fault model for the Nanoscale Application Specific Integrated Circuits (NASIC) fabric that can determine probabilities of output faults taking into account the defect scenarios, the logic and circuit style of the fabric as well as structural redundancy schemes that may be incorporated in the circuits. Evaluation of fault rates using the analytical model for single NASIC tiles show an inequality of the probability of output faulty ‘1’s and ‘0’s. To mitigate the effects of the unequal fault rates, biased voting schemes are introduced and are shown to achieve up to 27% improvement in the reliability of output signals compared to conventional majority voting schemes. NASIC circuits have to be cascaded in order to build larger systems. Furthermore, modular redundancy alone will be insufficient to tolerate high defect rates since multiple input modules may be faulty. Hence incorporation of structural redundancy is crucial. Thus in this thesis, we study the propagation of faults through a cascade of NASIC circuits employing the conventional structural redundancy scheme which is referred to here as the Regular Structural Redundancy. In our analysis we find that although circuits with Regular Structural Redundancy achieve greater signal reliability compared to non-redundant circuits, the signal reliability rapidly drops along the cascade due to an escalation of faulty ‘0’s. This effect is attributed to the poor tolerance of input faulty ‘0’s exhibited by circuits with the Regular Structural Redundancy. Having identified this, we design a new scheme called the Staggered Structural Redundancy prioritizing the tolerance of input faulty ‘0’s. A cascade of circuits employing the Staggered Structural Redundancy is shown to maintain signal reliability greater than 0.98 for over 100 levels of cascade at 5% defect rate whereas the signal reliability for a cascade of circuits with the Regular Structural Redundancy dropped to 0.5 after 7 levels of cascade.Master of Science in Electrical and Computer Engineering (MSECE
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Towards Logic Functions as the Device using Spin Wave Functions Nanofabric
No full textAs CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices. Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm that enables realization of arbitrary logic functions (with high fan-in/fan-out) more efficiently. We leverage on non-equilibrium spin wave physical phenomenon and wave interference to realize these elementary functions called Spin Wave Functions (SPWFs). In the proposed fabric, computation is based on the principle of wave superposition. Information is encoded both in the phase and amplitude of spin waves; thereby providing an opportunity for compressed data representation. Moreover, spin wave propagation does not involve any physical movement of charge particles. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. We show several variants of the SPWFs based on topology, signal weights, control inputs and wave frequencies. SPWF based designs of arithmetic circuits like adders and parallel counters are presented. Our efforts towards developing new architectures using SPWFs places strong emphasis on integrated fabric-circuit exploration methodology. With different topologies and circuit styles we have explored how capabilities at individual fabric components level can affect design and vice versa. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, up to 40x reduction in area and 228x reduction in power is possible. For the 2-bit adder, results show that up to 33x area reduction and 222x reduction in power may be possible. Building large scale SPWF-based systems, requires mechanisms for synchronization and data streaming. In this thesis, we present data streaming approaches based on Asynchronous SPWFs (A-SPWFs). As an example, a 32-bit Carry Completion Sensing Adder (CCSA) is shown based on the A-SPWF approach with preliminary power, performance and area evaluations.Master of Science (M.S.
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Multi-Valued Majority Logic Circuits Using Spin Waves
No full textWith increasing data sets for processing, there is a requirement to build faster and smaller arithmetic circuits. One of the ways to improve the performance of higher order arithmetic units is to reduce the carry propagation levels. Multi-valued logic enables this by reducing the number of digits required to represent a range of numbers. Area reduction is also obtained through fewer operations and signals required to realise a function. Though theoretically multi-valued logic has these advantages, implementation of the multi-valued logic using CMOS has not been efficient. The main reason is because multi-valued logic is emulated in CMOS using binary switches. Two main approaches are followed in CMOS in implementing multi-valued logic using CMOS. Voltage mode logic, where the logic states are encoded using the node voltages suffer from low noise margins and limitation of radix due to the power supply. Current mode logic, where the branch currents are used to represent the logic levels suffer from high power consumption due to static current flow and requirement of restoration devices. The mindset of the post-CMOS approaches explored so far for multi-valued logic circuit design has been to replace the CMOS switches with their novel nano switches. Hence they too suffer from the same issues as CMOS implementation. Our value proposition is through the use of a truly multi-state device based on electron spin. Spin waves, which are a collection of electron spins of an atom enables multi-valued logic by allowing encoding information in the amplitude and phase of the wave.Another advantage of the spin wave fabric is that the computation is through wave propagation and interference which does not involve any movement of charge. This enables building low energy,smaller and faster multi-valued circuits. In this thesis, implementation of the basic building blocks of multi-valued logic using these novel spin wave based devices is shown. Building of arithmetic circuits like adders using these building blocks have also been demonstrated. To quantify the benefits of spin wave based multi-valued circuits, they are benchmarked with CMOS. For 32-bits, our projected comparisons show a 5X increased performance, 125X area improvement and 1717X power reduction for hexa-decimal spin wave based adders compared to binary CMOS. Similarly there is a 4X increase in performance of hexa-decimal SPWF multiplier compared to CMOS for 16 bits. Finally, we have implemented the I/O circuits for smooth interface between binary CMOS and multi-valued SPWF logic.Master of Science in Electrical and Computer Engineering (MSECE
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SkyNet: Memristor-based 3D IC for Artificial Neural Networks
No full textHardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs. This work proposes a new fine-grained 3D integrated circuit technology for ANNs that is one of the first IC technologies for this purpose. Synaptic weights implemented with devices are incorporated in a uniform vertical nanowire template co-locating the memory and computation requirements of ANNs within each neuron. Novel 3D routing features are used for interconnections in all three dimensions between the devices enabling high connectivity without the need for special pins or metal vias. To demonstrate the proof of concept of this fabric, classification of binary images using a perceptron-based feed forward neural network is shown. Bottom-up evaluations for the proposed fabric considering 3D implementation of fabric components reveal up to 19x density, 1.2x power benefits when compared to 16nm hybrid memristor/CMOS technology.Master of Science (M.S.
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Architecting SkyBridge-CMOS
No full textAs the scaling of CMOS approaches fundamental limits, revolutionary technology beyond the end of CMOS roadmap is essential to continue the progress and miniaturization of integrated circuits. Recent research efforts in 3-D circuit integration explore pathways of continuing the scaling by co-designing for device, circuit, connectivity, heat and manufacturing challenges in a 3-D fabric-centric manner. SkyBridge fabric is one such approach that addresses fine-grained integration in 3-D, achieves orders of magnitude benefits over projected scaled 2-D CMOS, and provides a pathway for continuing scaling beyond 2-D CMOS. However, SkyBridge fabric utilizes only single type transistors in order to reduce manufacture complexity, which limits its circuit implementation to dynamic logic. This design choice introduces multiple challenges for SkyBridge such as high switching power consumption, susceptibility to noise, and increased complexity for clocking. In this thesis we propose a new 3-D fabric, similar in mindset to SkyBridge, but with static logic circuit implementation in order to mitigate the afore-mentioned challenges. We present an integrated framework to realize static circuits with vertical nanowires, and co-design it across all layers spanning fundamental fabric structures to large circuits. The new fabric, named as SkyBridge-CMOS, introduces new technology, structures and circuit designs to meet the additional requirements for implementing static circuits. One of the critical challenges addressed here is integrating both n-type and p-type nanowires. Molecular bonding process allows precise control between different doping regions, and novel fabric components are proposed to achieve 3-D routing between various doping regions. Core fabric components are designed, optimized and modeled with their physical level information taken into account. Based on these basic structures we design and evaluate various logic gates, arithmetic circuits and SRAM in terms of power, area footprint and delay. A comprehensive evaluation methodology spanning material/device level to circuit level is followed. Benchmarking against 16nm 2-D CMOS shows significant improvement of up to 50X in area footprint and 9.3X in total power efficiency for low power applications, and 3X in throughput for high performance applications. Also, better noise resilience and better power efficiency can be guaranteed when compared with original SkyBridge fabrics.Master of Science in Electrical and Computer Engineering (MSECE
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Built-In Fault Masking For Defect Tolerance And Parameter Variation Mitigation In Nano-Processors
No full textNanoscale manufacturing techniques enable very high density nano fabrics but may cause orders of magnitude higher levels of defects and variability than in today‟s CMOS processes. As a result, nanoscale architectures typically introduce redundancy at multiple levels of abstractions to mask faults. Schemes such as Triple Modular Redundancy (TMR) and structural redundancies are tailored to maximize yield but can impact performance significantly. For example, due to increases in circuit fan-in and fan-out, a quadratic performance impact is often projected. In this thesis, we introduce a new class of redundancy schemes called FastTrack, designed to provide fault tolerance but without their negative impact on performance. FastTrack relies on combining non-uniform structural redundancy with uniquely biased nanoscale voters. A variety of such techniques are employed on a Wire Streaming Processor (WISP-0) implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) nanowire fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates. Most importantly, the yield improvement is achieved in conjunction with 79% lesser performance impact at 10% defect rate. This is the first redundancy scheme we are aware of to achieve such degree of fault masking without the considerable performance impact of conventional approaches. The same setup is also used to mask the effects of parameter variation. FastTrack techniques show up to 6X performance improvement compared to more traditional redundancy schemes even at higher defect rates. In the absence of defects, a FastTrack scheme can be up to 7X faster than a traditional redundancy scheme.Master of Science (M.S.
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Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric
Get PDFCMOS SRAM area scaling is slowing down due to several challenges faced by transistors at nanoscale such as increased leakage. This calls for new concepts and technologies to overcome CMOS scaling limitations. In this thesis, we propose a multi-state memory to store multiple bits in a single cell, enabled by graphene and graphene nanoribbon crossbar devices (xGNR). This could provide a new dimension for scaling. We present a new multi-state volatile memory fabric called Graphene Nanoribbon Tunneling Random Access Memory (GNTRAM) featuring a heterogeneous integration between graphene and CMOS. A latch based on the xGNR devices is used as the memory element which exhibits 3 stable states. We propose binary and ternary GNTRAM and compare them with respect to 16nm CMOS SRAM and 3T DRAM. Ternary GNTRAM (1.58 bits/cell) shows up to 1.77x density-per-bit benefit over CMOS SRAMs and 1.42x benefit over 3T DRAM in 16nm technology node. Ternary GNTRAM is also up to 1196x more power-efficient per bit against high-performance CMOS SRAMs during stand-by. To enable further scaling, we explore two approaches to increase the number of bits per cell. We propose quaternary GNTRAM (2 bits/cell) using these approaches and extensively benchmark these designs. The first uses additional xGNR devices in the latch to achieve 4 stable states and the quaternary memory shows up to 2.27x density benefit vs. 16nm CMOS SRAMs and 1.8x vs. 3T DRAM. It has comparable read performance in addition to being power-efficient, up to 1.32x during active period and 818x during stand-by against high performance SRAMs. However, the need for relatively high-voltage operation may ultimately limit this scaling approach. An alternative approach is also explored by increasing the stub length in the xGNR devices, which allows for storing 2 bits per cell without requiring an increased operating voltage. This approach for quaternary GNTRAM shows higher benefits in terms of power, specifically up to 4.67x in terms of active power and 3498x during stand-by against high-performance SRAMs. Multi-bit GNTRAM has the potential to realize high-density low-power nanoscale memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.Master of Science in Electrical and Computer Engineering (MSECE
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N3asics: Designing Nanofabrics with Fine-Grained Cmos Integration
No full textNanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems. We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N3ASICs with no new manufacturing constraints. In N3ASICs active devices are formed on a dense semiconductor nanowire array and standard area distributed pins/vias, metal interconnects route signals in 3D. The proposed N3ASICs fabric is fully described and thoroughly evaluated at all design levels. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling. Overall N3ASICs fabric design, associated circuits, interconnection approach, and a layer-by-layer assembly sequence for the fabric are introduced. System level metrics such as power, performance, and density for a nanoprocessor design built using N3ASICs were evaluated and compared against a functionally equivalent CMOS design. We show that the N3ASICs version of the processor is 3X denser and 5X more power efficient for a comparable performance than the 16-nm scaled CMOS version without any new/unknown-manufacturing requirement. Systematic yield implications due to mask overlay misalignment have been evaluated. A partitioning approach to build complex circuits has been studied.Master of Science in Electrical and Computer Engineering (MSECE
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