605 research outputs found
THE HUMAN PERSONALITY IN THE WORKS OF L.K. IVANOV
No full textВ статье рассматривается личность человека на примере произведений Леонида Кирилловича Иванова. В настоящее время изучение личности является актуальной проблемой в современной литературе, так как многие годы объектом исследования в советской литературе был не человек как личность, а человек как ячейка общества. Автор анализирует рассказы Л.К. Иванова и исследует личность главных героев.In the article the human personality on the basis of Leonid Kirillovich Ivanov’s works is considered. At present, the study of human personality is an important problem in modern literature, as the object of research for many years in Soviet literature was not a man as a person, and the person as a social unit. The author analyzes L.K. Ivanov’s stories and investigates the human personality of the main characters
Discrete Darboux based fast inverse nonlinear Fourier transform algorithm for multi-solitons
No full textA fast algorithm for constructing multi-solitons with linear complexity in the number of samples and eigenvalues is introduced. The algorithm is shown to be significantly faster than the conventional Darboux transform in a numerical example, with acceptable error.Accepted Author ManuscriptTeam Raf Van de PlasTeam Sander Wahl
Radio galaxies at low frequencies: high spatial and spectral resolution studies with LOFAR
No full textThis thesis uses novel observations from the Low Frequency Array to address open questions on the topic of galaxy evolution. The highest resolution images at ultra low radio frequencies are used to investigate the physical processes present in the radio emission from distant galaxies. Detections of spectral features from carbon atoms in a nearby galaxy are also presented and used to constrain the temperature and density of cold gas that is a key component of all galaxies
Aluminum-Mediated Selective Solid-Phase Epitaxy of High-Quality Silicon Diodes
No full textElectrical Engineering, Mathematics and Computer Scienc
Silicon Technology for Integrating High-Performance Low-Energy Electron Photodiode Detectors
No full textECTMElectrical Engineering, Mathematics and Computer Scienc
Interface Properties of Group-III-Element Deposited-Layers Integrated in High-Sensitivity Si Photodiodes
No full textIn this thesis, the research on silicon-based CMOS-compatible PureB technology was continued with the goal of enabling a PureB process module that could be added as a back-end module to wafers from a CMOS foundry. The properties of PureB layers deposited at low-temperature, particularly those deposited at 400°C were studied in more detail, among other things by introducing new electrical test structures. A new deposition method including gallium deposition, called PureGaB, was developed to alleviate some of the difficulties encountered when reducing the deposition temperature. Moreover, the capabilities of PureB technology were extended by a demonstration of highly-sensitive single-photon avalanche diodes (SPADs).ECTMElectrical Engineering, Mathematics and Computer Scienc
DotFETs: MOSFETs strained by a Single SiGE dot in a Low-Temperature ELA Technology
No full textThe work presented in this thesis was performed in the context of the European Sixth Framework Program FP6 project “Disposable Dot Field Effect Transistor for High Speed Si Integrated Circuits”, referred to as the D-DotFET project. The project had the goal of realizing strain-enhanced mobility in CMOS transistors by transferring strain from a self-assembled germanium dot to the channel of a transistor fabricated above the dot. The initial idea was to dispose of the Ge dot underneath the channel after the gate processing so that the gate-stack would also serve to stabilize the channel-bridge and maintain the strain induced in the channel silicon by the Ge dot. The advantage of using a SiGe dot as a strain source is its scalability to as low as 10 nm gate dimensions, which is not obvious for currently used methods for imparting strain on the Si channel. Furthermore, the D-DotFET structure offers advantages for the electrostatic and electrothermal behavior of MOS devices. For example, SOI devices with fully-depleted channel are a solution for short-channel effects but the insulating oxide beneath the device introduces a thermal management issue. This problem is solved in Silicon-on-Nothing (SON) devices because the insulating region is then only found under the gate with the source and drain regions still being anchored to the thermally conductive bulk silicon. The D-DotFET resembles the SON transistor but with the added advantage of strain-enhanced device gain and speed. In that way the D-DotFET combines four potential improvements: strain enhanced performance, scalability to future ~ 10 nm generations, suppression of short-channel effects, and good heat dissipation. Research was done in several areas to assure that the stringent requirements on uniformity, reproducibility and reliability could potentially be met to transfer the D-DotFET concept to advanced CMOS. The growing of silicon germanium (SiGe) dots with the necessarily high Ge content was first developed, and uniformity and reproducibility were brought to a high level of perfection. The strain of both bare and overgrown dots was extensively analyzed both experimentally and theoretically. Then, the strain that could be transferred to the channel of a MOSFET was evaluated in terms of mobility enhancement via device simulations, and lastly, the actual integration of dots was demonstrated in a low-complexity n-MOSFET research process that was specially tailored to this application, which is the topic of this thesis. The Dimes cleanrooms were not equipped to set up a state-of-the-art CMOS process to investigate the D-DotFET concept. However, the available expertise and equipment was suitable for running a more advanced process, where excimer laser annealing could be implemented to replace the standard rapid thermal annealing and a metal gate could replace the standard polysilicon gate. Furthermore, the patterning of ~ 100 nm gate features was performed by e-beam lithography by the project partner Forschungszentrum Jülich. To avoid as many nanoscale lithography steps as possible, geometry with large source-drain contacting areas was devised so that only one step, the ~ 100 nm gate definition itself, needed to be patterned by e-beam. Additionally, since the goal was in first instance to verify the strain-enhanced gain induced by the dot, it was decided to significantly simplify the transistor processing by retaining the dot throughout. A “DotFET” rather than a “D-DotFET” was therefore fabricated. This meant that only low-temperature processing steps could be performed after the dot formation, in order to avoid intermixing of Si and Ge and consequent strain relaxation. This was realized in a dedicated n-MOSFET process where the temperature was kept below 400?C after epitaxy by using low-temperature gate dielectrics and a metal gate self-aligned to implanted and laser annealed source/drain regions. The SiGe dots used for the DotFET fabrication were grown in a self-assembling Stranski-Krastanow mode that allows single-crystalline dots of SiGe to grow in three-dimensions on predefined seedholes. Under appropriate conditions this growth is defect free and can easily be scaled down. The 3D growth of the SiGe allows a higher Ge content inside the dot before the onset of crystal dislocations as compared to the growth of 2D SiGe layers of similar thickness. The smaller the SiGe dots the higher the Ge content that can be maintained without defect formation and consequently a higher strain can be exerted on any Si layer grown over the dot. For the devices described in this thesis, the dots were grown by MBE on a regular seedhole pattern of submicron periodicity etched into the Si. The growth was investigated in detail to determine the optimum growth conditions and seedhole-patterns for achieving a dot-size and strain level suitable for constructing a MOSFET over the center of the dot structure where the biaxial tensile strain could be exploited for channel mobility enhancement. For a uniform and reproducible SiGe dot growth, excellent results were achieved by a location-controlled growth method where large, regular arrays of seedholes are patterned on an otherwise flat Si substrate. In the present work, both i-line optical lithography and e-beam lithography (EBL) were used to pattern such holes in (100) Si wafers. In the case of e-beam lithography a very good control of the seedhole positions and size is obtained and the resulting dots are extremely regular. The present DotFET fabrication required a dot size that could accommodate a gate of length ~ 100 nm. For this purpose the most suitable seedhole arrays were the ones with a periodicity of 800 nm that rendered a maximum dot diameter in the range of 230 nm. EBL patterning of this configuration was used for the device fabrication, while analysis of the dot properties was also performed on samples processed with optical lithography. The growing of the dots on the seedhole pattern starts with the deposition of a Si buffer layer which smoothes the surface. The dots are then grown at 720?C from a pure Ge source In Chapter 2, a simple, low-temperature process flow for achieving good quality ultrashallow n+p junction diodes has been demonstrated for 5 keV As+ implants activated by excimer laser annealing. Much research has recently been done using ELA techniques due to the extremely short annealing times that potentially eliminate transient enhanced diffusion effects, reach high levels of dopant activation and give abrupt junctions. Compared to conventional rapid thermal anneal procedures ELA offers the advantage of a good control of the junction depth, where a reduction of the vertical implantation range can serve as a direct means of also decreasing the junction depth. The laser processing research performed at Dimes in the past, rather than being aimed at the fabrication of source and drain regions for CMOS, has been motivated by the need to have access to good quality diodes in integration situations where only very low temperatures are permitted, such as in silicon-on-glass processing. With respect to the bulk laterally-uniform part of the diode away from the perimeter, it is important that the Si-surface to be implanted is smooth and native-oxide free before implantation. The implant needs to be so shallow that the melt region encompasses the whole implanted region but deep enough to avoid laser-induced-surface-structuring effects on the Si surface from affecting the underlying metallurgic junction region. Tilted implants can reduce the final junction depth of the 5 keV implants to below 20 nm. With respect to the perimeter of the diode, the key to achieving diodes of good quality is the termination of the metallurgic junction at an oxide-to-silicon interface that is of good quality. In the presented experiments this is achieved by using a thin layer of thermal oxide to cover the Si under a thicker low-temperature isolation layer. The oxide at the interface is a 30-nm-thin layer of thermal oxide, which is still sufficiently thick to avoid excessive widening of the contact window during the dip-etch used to remove native oxide before metallization. After the growth of the isolation oxide, all processing steps are performed at temperatures below 400ºC. A reflective mask of Al is applied to localize the laser melting of the silicon to the desired diode region and to protect the perimeter. The tilted implants also increase the overlap of the oxide isolation with the diode perimeter, making the process more robust which in turn reduces perimeter leakage. The completeness of the laser melt at the perimeter depends on the thermal conductivity of the surroundings. Less melting of the perimeter with respect to the bulk is identified by TEM analysis in diodes processed in Dimes and this may be a source of extra perimeter leakage that needs to be taken into account when designing a specific process flow and diode structure. The best results are achieved here with an implant of 2x1015 cm-2 at tilt of 30?. For diodes with an area of 80 ?m2 this gives an ideality factor of 1.04 and reverse leakage at 2 V in 10-5 A/cm2 range. The low-temperature processing needed for the DotFET transistor puts heavy demands on the processing temperature of the gate dielectric which conventionally is a high-quality thermal oxide grown at temperatures above 850?C. In Chapter 3 a study is presented of a number of dielectric layer-stacks formed at temperatures below 400?C that could potentially be used as DotFET gate material. MIS capacitors were fabricated with different gate- dielectric layer stacks and electrically characterized, and a comparison was made to capacitors with a SiO2 interface layer thermally-grown at ? 700?C. It was chosen to investigate atomic-layer deposited Al2O3 layers because this technique gives an excellent uniformity, conformality, precise control of the thickness of the films, and it is possible to deposit high-quality layers at low temperature. Cycles of TMA and water were applied in order to deposit the Al2O3 layers at a temperature of 300?C. The SiOxNy films with a low concentration of N were grown by inductively coupled plasma at a temperature of 250?C. The results of capacitance-voltage and current-voltage measurements demonstrated that ALD Al2O3 and ICP SiOxNy exhibited a dielectric constant of 4 and 8, respectively. With ICP SiOxNy, capacitors were fabricated with low interface trap level density and low effective charge density, < 1011 cm-2eV-1 and <1011 cm-3eV-1, respectively, as well as low leakage current density (< 10-7 A/cm2). For pure Al2O3 layers the interface quality to Si was poor and in order to improve this situation, a high-quality interface layer was either grown or deposited between the alumina and Si substrate. Due to the simple, fast processing and good quality of the ICP SiOxNy dielectric at low temperature, the SiOxNy was finally chosen for the fabrication of the MOSFETs and DotFETs. The processing techniques for the fabrication of n+p diodes with ultrashallow junction annealed by excimer laser technique and capacitors using Al2O3 and SiOxNy gate dielectrics were combined to create a simple MISFET device presented in Chapter 4. The fabrication of n- and p-MISFET devices was demonstrated for processing temperatures below 400?C. Four important processing steps need to be performed in order to have good electrical device performance: (i) for a good quality growth of ICP-SiOxNy, the Si surface must be cleaned immediately before the growth, achieved with a HF dip-etch; (ii) a dip in BHF is performed immediately before source/drain implantation to remove the native oxide on the Si surface and achieve a uniform implantation of the low-energy ions; (iii) a RIE process with low RF power is used for oxide etching to open the source/drain contact windows in order to reduce damage to the implanted silicon surface; (iv) a HF dip-etch is used to remove native oxide before source/drain metallization and ensure a low-ohmic contacting. Both n- and p-MISFET devices show good performance, especially with respect to drain current driving capability. By increasing the laser energy, the sheet resistance of source/drain regions is reduced due to higher dopant activation. The source to drain resistance was also extracted from the measurements and an increase was observed when the channel length increases. Ultrashallow source/drain junctions were activated and the TEM images show junctions of 10-12 nm deep for 1000 mJ/cm2 laser energy. The overlapping of the laser spot was studied for 66% and 1% overlap. The drain current is higher for 66% overlap, again due to higher dopant activation but at a cost of some extra heating. In Chapter 5, the demonstration of high performance n-DotFET devices, successfully fabricated by adapting the n-MISFET process to the dot structure, is presented. Transistors with a minimum gate-length dimension of 50 nm using TiN/Al(1%Si) metal-gates were processed. A SiGe dot grown by MBE was used as stressor material. The best energies for excimer laser annealing of these structures were found to be between 850 mJ/cm2 and 900 mJ/cm2. E-beam lithography was used to define nanoscale gate dimensions in the central region of the dot and a 1-µm-wide gate finger is defined to contact this narrow gate. Thus a part of the current between the source and drain flows around the dot structure rather than through the silicon channel over the SiGe dot. Despite this effect, it is still possible to determine the influence of the strain on the drain current. The electrical characteristics show a drain current enhancement between 2% and 35%. The simulations show enhancements due to the strained Si layer of 20% - 22%. The small dimensions of the channel result in a large spread of measured characteristics, but nevertheless, the impact of the strain Si layer can be indentified. On a test sample the SiGe dot was removed using ammonium hydroxide, hydrogen peroxide and deionized water, which shows the possibility of fabricating a D-DotFET device in the future. Simulations of D-DotFETs and DotFETs fabricated on SOI substrates were done and the results show a reduction of self-heating for D-DotFET devices. Conclusions to the thesis are given in Chapter 6. The two most important results of this thesis are the demonstration of the applicability of (1) SiGe dots as stressor material and (2) full-melt high-power laser annealing as a technique for lowering the source/drain series resistance in a manner self-aligned to the gate.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Excimer laser annealing for ultrashallow junctions and contacts
No full textElectrical Engineering, Mathematics and Computer Scienc
Silicon doping techniques using chemical vapor dopant deposition
No full textUltrashallow junctions are essential for the achievement of superior transistor performance, both in MOSFET and bipolar transistors. The stringent demands require state-of-the-art fabrication techniques. At the same time, in a different context, the accurate fabrication of various n type doping profiles by low-temperature Si epitaxy is a challenge due to autodoping. In this thesis, these two, apparently unrelated, problems are both addressed as the layer of CVD surface-deposited dopant atoms is used as a doping source. It is demonstrated that a layer of dopants deposited on the Si surface can be used as a doping source by either thermal or laser drive-in for the fabrication of both deep and ultrashallow defect-free junctions. In low-temperature CVD epitaxy, autodoping is a consequence of dopant surface segregation and doping from the surface layer. This process has been characterized, and consequently excellent controllability is achieved. In addition, new results related to the CVD of dopants itself are obtained, and two theoretical achievements are made: the analytical model of arbitrarily shallow junctions is derived, and a new C-V profiling technique suitable for the characterization of ultrashallow junctions is developed. The analytical model of arbitrarily shallow junctions, presented in Chapter 2, is derived based on the basic transport mechanisms, with the junction depth as a free parameter, allowing the junction to be fully depleted or disappear. In this way, a closed-form model is obtained that unifies the standard p-n junction and Schottky junction models. With such a unified description, the characteristics of extremely shallow diodes that lie at the cross-over between the standard p-n and Schottky diodes are for the first time analytically described, and new phenomena are observed: both forward and reverse characteristics exhibit specific nonidealities. In that respect, this model can be used to predict the onset of nonidealities as a function of the doping levels, junction depth and biasing conditions. The process of dopant CVD is central to the experimental work presented in this thesis, and it is described in detail in Chapter 3, together with other experimental techniques. Particular focus is given to the deposition of As, the deposition dynamics of which have been empirically modeled to enable accurate sub-monolayer deposition at 800 °C, and the ability to achieve substantial deposition has been demonstrated down to 300 °C. The high-temperature step prior to deposition was found to be unnecessary if Marangoni drying is used. Also, techniques for the removal of As have been investigated: thermal desorption and different wet cleaning solutions. With dopant CVD and drive-in, there are two high-temperature steps to which windows in SiO2 to the Si are exposed: first, for surface cleaning before dopant deposition, and second, for dopant drive-in; and both can have detrimental effects on the definition of deposition windows and on the Si surface. The kind and extent of disfiguration that appears in these two processes has been described in Chapter 4. At temperatures above 900 °C, significant lateral widening of deposition windows is observed. At 1100 °C, also micrometer-deep cavities in the Si form. These spikes typically form in the corners or around the edges of deposition windows, and their generation is catalyzed by the presence of dopants. Contrary to the CVD of B, As and P depositions are limited to a maximum of a single monolayer. This is nevertheless a substantial dose, well suited for the ultrashallow junction formation, which has been demonstrated by thermal and laser drive-in, and the results are presented in Chapter 5. Thermal diffusion was characterized in the temperature range from 700 °C to 900 °C. Due to the high concentration gradient, low diffusivity and SiO2 encapsulation, nanometer-shallow junctions are formed, while no defects are introduced. The diffused dose, however, is only a fraction of a monolayer, and the junctions can even be fully depleted, exhibiting characteristics predicted by the model of arbitrarily shallow junctions. Nevertheless, they can be very effective in modulating the effective Schottky barrier height. With laser annealing, at laser energy densities above the Si melt limit, successful drive-in of the complete monolayer is achieved. Thereby, junctions 10 nm to 15 nm deep, with 3 nm/dec or better vertical abruptness, doped above 3x10^20 cm-3, with sheet resistance around 300 ohm/sq indicative of 100% activation are formed in an essentially room-temperature process. Such exceptionally good results are enabled by the fact that the defect-inducing ion implantation is not used, thus no defect annealing steps are needed. While the doping profiles satisfy the ITRS requirements, the low defect density and low processing temperature make this, in combination with As deposition at 300 °C, a promising solution for junction formation after metallization and for backside junction formation in the SOG substrate-transfer technology. For the low-temperature RPCVD Si epitaxy, an empirical model of As surface segregation, adsorption, and incorporation from the surface layer has been developed, and is presented in Chapter 6. Together with the pure As deposition and As wet chemical removal, this model enables very accurate fabrication of doping profiles of nearly arbitrary shape, the most important restriction being that the profiles can be both continuously or discretely increasing in the growth direction, but only discretely decreasing using ex-situ As cleaning. Based on this model, profiles inversely proportional to the square of the doping depth are fabricated for the novel varactor diodes with state-of-the-art linearity. For the purpose of characterization of ultrashallow junctions, beyond the limitations of SIMS resolution, a new C-V profiling technique has been developed and is presented in Chapter 7. It relies on fabricating and measuring two diodes, one Schottky and one p-n diode, both with the same background doping profile, in order to obtain first the background and then the ultrashallow doping profile. It has been demonstrated that this can be achieved if the background profile contains abrupt changes in doping, e.g. in the form of steps, even if it is considerably less abrupt and less highly doped. Using an epitaxially grown step-like background profile, the ultrashallow B profile formed only by pure B CVD has been measured to have the junction depth of 7 nm, and the slope of around 2.5 nm/dec.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Characterization of pure boron depositions integrated in silicon diodes for nanometer-deep junction applications
No full textDoping technologies for formation of ultrashallow and highly-doped p+ junctions are continuously demanded to face the challenges in front-end processing that have emerged due to the aggressive downscaling of vertical dimensions for future semiconductor devices. As an alternative to implantations, current solutions are based on in-situ boron (B) doping during Si/SiGe chemical vapor deposition (CVD) by using diborane (B2H6) as the dopant gas. In this context, a few studies have demonstrated p+-like doping behavior of n-type (100)-oriented Si surfaces after exposure solely to B2H6 in an oxygen-free atmosphere without any extra addition of silane-based sources. As illustrated in Chapter 1, this doping process relies on the thermal decomposition of the source gas, so that the available boron atoms may stick to the surface, chemically react with silicon atoms, and diffuse into the substrate. Contrary to other doping impurities, by appropriately varying the source gas parameters and the exposure time, the reaction kinetics can also cause the boron density at the silicon surface to significantly increase beyond the solid solubility in Si at the given processing temperature. Thus, a boron layer can be formed. However, this property has not been explored so far with respect to reliable integration in Si-based device technologies, since boron segregation has been commonly addressed as a drawback of this doping method. This thesis presents the characterization of nanometer-thick B-layers formed during exposure to diborane in a commercially available CVD system at either atmospheric or reduced pressures down to 500C by using B2H6 at high concentrations. The process, as described in Chapter 2, substantially differs from previous approaches both with respect to the low temperature used and the gas exposure conditions. The former is generally very attractive for versatile use of a doping technology, while the excessive B adsorption intentionally promoted on the Si surface, i.e. the deposition of a B-layer, is demonstrated to offer unprecedented advantages for the formation of ultrashallow and low leakage pn-junctions. Analytical techniques, such as transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), in conjunction with an extensive electrical characterization are applied to investigate the material and electrical properties of the B-layers as a function of the deposition conditions. The experimental results are also validated by process and device simulations. The formation of B-layers is slower the lower the temperature and the diborane partial pressure, and mainly controlled by the exposure time at high gas flow rates that provide good conditions for segregation of boron atoms on the Si surface. While gas parameters can determine the transition from surface Si doping to B-deposition, the temperature mainly influences the final composition of the deposited film that can vary from amorphous boron (a-B) to a boron-silicon compound, i.e. boron-silicide, (BxSiy), for temperatures increasing from 500C to 800C. The deposition exhibits high selectivity to Si, isotropy, and uniformity for any surface topography and patterning. The time dependence of the B-layer growth is quite linear and a similar grading coefficient is observed for the boron surface density. The chemical reactivity of boron with HNO3-based acid solutions can be used for the removal of the layer. Furthermore, the growing B-film will act as a source for boron thermal diffusion during the CVD process itself, and the crystalline Si substrate is p-doped up to the B solid solubility. The as-diffused active boron density is also shown to be quantitatively controlled by the exposure time. Moreover, both the relatively low deposition temperature and the absence of any defect formation, which could cause enhanced-diffusion effects, ensure junction depths lower than 10 nm even after prolonged depositions. In Chapter 3, the properties of the deposited B-layers are further explored with respect to formation of high-quality, ultrashallow junctions in p+n diode configurations. Ohmic contacts, diodes, and pnp bipolar structures are fabricated and characterized under different B2H6 exposure conditions. As B-deposition is commenced, the Fermi level of the exposed Si surface is rapidly shifted towards the valence band, as one would expect for electrically active p-type doping. This is beneficial for formation of very low-ohmic contacts on p-type surfaces, while pn diodes are formed on n-type Si substrates. In the latter case, the near-ideal saturation current can be tuned from high Schottky-like values to low deep-pn-junction-like values by increasing the deposited B-layer thickness by just a few nm. The integration of B-deposited emitters in pnp structures has shown that the presence of a distinct a-B layer, which occurs for min-long exposures, is an effective way to suppress the electron minority carrier injection from the n-substrate. This results in an effective Gummel number 60 times higher than that of the diffused emitter only. The doping efficiency is also demonstrated to be superior to that in conventional B-doped Si epitaxy and comparable to B+ / BF2+ ion implants. Although for increasing thickness the series resistance through this high-resistive layer will eventually dominate the I-V behavior, processing conditions can be found where exceptionally low values of both series resistance and saturation current can be achieved. However, the high-ohmic property can be used as a means of fabricating very compact, small area, and non-linear resistors. The compatibility of the doping technique with standard Si device manufacturing is also proven. Also for the use of hard-mask materials other than SiO2 the selectivity of the B-layers to deposit only in the contact openings to the Si has been demonstrated. Furthermore, due to the excellent isotropic coverage, the B-deposition can be applied to non-planar device schemes such as trenches and recessed-contact technologies. Although the boron chemical concentration significantly exceeds the solid solubility at the silicon surface, for as-deposited B-layers the active dopants of the c-Si substrate is found to be essentially limited by substitutional incorporation at the deposition temperature. However, in Chapter 4 the B-layer is demonstrated to act as a well-controlled source of dopant for solid-phase diffusion during any subsequent in-situ or ex-situ high-temperature annealing step. The presence of a sufficiently thick B-layer offers, due to its thermal stability, the additional advantage of being able to minimize boron evaporation. Thus, a higher dopant activation can be obtained with a good control of the resulting junction depth. Furthermore, the use of B2H6 exposure and thermal anneal as post-processing gives more insights into the influence of processing parameters on the boron adsorption mechanism. In particular, at very low temperatures, hydrogen termination of the silicon surface is assumed to influence the sticking of boron atoms. In this respect, the carrier gas can play a significant role. Finally, thermal anneals are also applied to increase the doping efficiency of B-layers that act as emitters in pnp bipolar transistors. The unique properties of the boron CVD deposition are exploited with great advantages in p+n diodes fabricated at 700C for the integration of two distinct device technologies: varactor diodes for adaptive functions in radio frequency (RF) applications and photodiodes for detection of ultraviolet (UV) radiation. In the former case, B-deposition offers a defect-free, low-temperature process module within the silicon-on-glass (SOG) substrate-transfer technology to form one-sided p+n-junctions that can preserve hyper-abrupt arsenic profiles needed for highly-linear tunable varactors. On the other hand, the fundamental advantages of the B-layers for use as a novel p+ front-layer in UV detectors are given by the extremely ultrashallow and highly-doped junction that is instrumental in the collection of the photogenerated carriers. Since both devices operate in reverse biasing mode, in Chapter 5 the electrical performance of the B-layers is investigated when reverse voltages are applied up to the expected diode breakdown limit. Device simulations demonstrate that the high electric field induced by the nm-deep p+ junction at the anode contact edges is responsible for band-to-band tunneling current. Thus, the reverse I-V characteristics of as-deposited B-doped varactors would suffer from high leakage current and premature breakdown. Diffused p+ guard-rings are proposed as a solution to reduce the electric field crowding at the contact rim. In addition, n+ channel-stop implants are used to prevent the depletion region from extending excessively under the MOS structure formed by the anode metallization on the SiO2 isolation layer and approach regions with reduced generation-recombination lifetimes. Then, the silicon-on-glass varactor technology is illustrated along with the electrical characterization results. A noteworthy improvement of the reverse I-V performance is shown for varactor implementations with either uniform or hyper-abrupt 1/x^2 As profiles when BF2+ and P+ implants are included in the process to form guard-rings and channel-stop regions, respectively. The devices have unprecedented low reverse current and an increased operating voltage range close to the theoretical breakdown limit. At the same time, the desired capacitance-voltage relationship is still preserved by the compatibility of the thermal processing steps with the As profiles. Chapter 6 describes the integration of B-layers in a silicon-based planar p+n photodiode technology for radiation detection in the complete UV spectral range down to soft X-ray wavelengths. The B2H6 exposure conditions for the formation of the sensitive surface are specifically optimized to minimize any possible quantum efficiency loss due to absorption and reflection of radiation in the front a-B layer. Without compromising the optical conversion efficiency, the B-deposition can be combined with in-situ thermal annealing and/or selective epitaxial Si growth to reduce the series resistance of the front p+ layer. An optical coating can also be integrated to either reduce reflection losses or determine a filtering radiation pass-band. Outstanding photodiode performance is achieved, since comparison with the state-of-the-art silicon detector technology shows that B-deposited devices perform with superior electrical and optical characteristics. In fact, they exhibit an ideal diode behavior with lower dark current. Furthermore, the extremely shallow front active p+ region offers higher sensitivity over a wider UV spectral range with excellent reproducibility. In particular, they show near a theoretical responsivity at short-wavelengths that is also very stable under high-dose radiation exposure. Finally, the main conclusions of the thesis are summarized in Chapter 7, which also provides recommendations for the future work. In particular, the research activity has shown that the B-layer can be seen as a new IC compatible doping material that owing to the unique properties can be both instrumental in the downscaling of bipolar/CMOS transistors and very attractive for many novel Si device configurations.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
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