1,721,069 research outputs found
The 2019 IEEE Computer Society: Hit Target on Member Satisfaction and Technical Excellence
No full textTechnology is rapidly evolving in computing and computing engineering; this continuously creates new opportunities for the advancement of science and humanity, but it also poses new scientific challenges. To maintain its leading role, the IEEE Computer Society (CS) must incorporate a dynamic evolution in all activities, products, and services, for the benefit of its members and humanity.
To meet this challenge, one year ago, in the Computer January 2019 issue, I presented member satisfaction and technical excellence as targets for my presidential year. Now, at the end of 2019, I am very glad and proud to announce that, with the cooperation of all CS constituencies and the IEEE, we have been able to hit all of them, and much more.
Particularly, at the beginning of 2019, together with the CS Board of Governors and staff, we defined the following shared goals to enable the CS to hit these targets: 1) increase member satisfaction; 2) enhance diversity, in gender, age, geographic location, and industry/academic affiliation; 3) boost technical excellence in all activities; 4) improve financial sustainability and transparency. Let me describe in more detail how we were able to reach each one of these goals
IEEE Transactions on Emerging Topics in Computing
No full textIEEE Transactions on Emerging Topics in Computing publishes papers on emerging aspects of computer science, computing technology, and computing applications not currently covered by other IEEE Computer Society Transactions
Bridging Faults in Pipelined Circuits Journal of Electronic Testing, Theory and Applications
No full textThis paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and Iddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
No full textThis paper analyses some of the most common error-detecting codes used in self-checking circuits with respect to the errors induced by crosstalk faults (CF's). The electrical-level behavior of circuits in the presence of CF's has been analyzed by considering these faults as parametric. A logic-level model providing the probability of errors has been abstracted and applied to the case of functional unit outputs (buses). Finally, the probability of detectable and undetectable errors has been evaluated for the parity, two-rail, m-out-of-n, and Berger codes, thus providing some design hint
Optimization of error detecting codes for the detection of crosstalk originated errors
No full textThis work applies weight based codes to the detection of crosstalk originated errors. This type of fault, whose importance grows with device scaling may originate errors that are undetectable by the commonly used error detecting codes in VLSI ICs. Conversely, such errors can be easily detected by weight based codes that, however, have smaller encoding capabilities. In order to reduce the cost of these codes, a graph theoretic optimization is used. Moreover new applications of these codes are explored regarding the synthesis of self-checking FSMs, and the detection of errors related to the clock distribution network. © 2001 IEEE
Pulse propagation for the detection of small delay defects
No full textThis paper addresses the problems related to resistive opens and bridging faults which cannot be detected using delay fault testing because they lie out of the most critical paths. Even if the induced defect is not large enough to result in timing violations, these faults may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capabity of faulty paths to propagate pulses. The effectiveness of the proposed method is analyzed at the electrical level and compared with the use of reduced clock period which can detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by problems on the clock distribution network. © 2007 EDAA
Online testing approach for very deep-submicron ICs
No full textVery deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach described by the authors can be exploited to detect stuck-at and bridging faults offlin
Single Output Distribute Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures
No full textThis paper proposes a distributed two-rail checker architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional two-rail checkers additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay faults
Problems due to open faults in the interconnections of self-checking data-paths
No full textIn this work, the problem of open faults affecting the interconnections of SC circuits composed by data-path and control is analyzed. In particular it is shown that, in case opens affect control signals, some problems may arise even if both control and data-path signals are concurrently checked. In particular, wrong codewords may be generated at the outputs of multiplexers and registers. To address this problem, new registers and multiplexers are proposed which allow the design data-paths which are TSC with respect to opens (and resistive opens). These components are also TSC with respect to stuck-at, transistor and gross delay faults. They present a good testability with respect to resistive bridgings. © 2002 IEEE
Novel low-cost aging sensor
No full textPerformance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming of great concern for current and future CMOS technology. Here we introduce an aging sensor able to detect such degradations in the combinational part of a critical data-path. It requires lower area than recently proposed alternative solutions, and a lower or comparable power consumption. © 2010 author/owner(s)
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