1,720,996 research outputs found
Static minimization of total energy consumption in memory subsystem for scratchpad-based systems-on-chips
No full textIn VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, and the memory sub-system can be responsible for up to 75% of the power. Scratch-pad memories (SPM) are a proven alternative to cache memories in power-aware SoCs. Optimal SPM mapping has already been investigated for dynamic power reduction in the main memory and for leakage reduction in the SPM itself. This paper addresses the problem of global energy optimization (i.e., active leakage) in the whole memory sub-system of an SPM-based SoC. We focus on SPMs dedicated to instructions and constant data. We present the technology-level foundation, the mathematical problem formulation, its solution as an integer-linear-programming (ILP) problem, the implemented design flow, and the power reduction results referring to standard benchmarks and ITRS technology data. © 2006 IEEE
Optimal pipeline stage balancing in the presence of large isolated interconnect delay
No full textPipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneously distributed. When the target microarchitecture design includes isolated long interconnects, such as buses, optimal pipeline stage balancing becomes a tricky problem. This work formalises the solution based on the logical effort paradigm and evidences its advantage with respect to a heuristic approach
Software Optimization of the JPEG2000 Algorithm on a VLIW CPU Core for System-on-Chip Implementation
No full textA class of code compression schemes for reducing power consumption in embedded microprocessor systems
No full textCompression of executable code in embedded microprocessor systems, used in the past mainly to reduce the memory footprint of embedded software, is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression, based on the concepts of static (using the static representation of the executable) and dynamic (using program execution traces) entropy and compare them with a state-of-the-art compression scheme, IBM's CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome of our work is that static compression is not directly related to bus traffic reduction, yet there is a trade off between static compression and dynamic compression, i.e., traffic reduction
Tiktak: A scalable simulator of wireless sensor networks including hardware/software interaction
No full textA platform-based emulator for mass-storage flash cards evaluation in embedded systems
No full textIn this work we present a simulation environment, built around the QEmu emulator, that allows the evaluation of mass-storage Flash-Card memories, specifically embedded Multimedia Cards (e-MMC). Flash card memories are internally complex systems containing, along with the memory array, an intelligent controller, running its own firmware. The controller is a critical unit, since its functions are not limited in providing a standard interface between the internal memory array and the user, but they are much more elaborate (e.g. buffering, erase sequences, garbage collection, flash memory wear leveling, etc.). It is then clear that the implementation of these functions can have a strong impact on performances. In this scenario, a simulation environment would be a valuable resource in the design flow, since it could allow the exploration of different internal architectures and firmware implementations, the verification and the estimation of performances of new devices during their design. Using QEmu as base environment, we have developed a fast emulator of a complete embedded system platform, containing a behavioral model of next-generation e-MMC devices, parametrized in order to be portable to future generations of e-MMCs. The whole emulator is fast enough to boot a complete Linux kernel and to launch applications, allowing the analysis of e-MMCs behavior on real use cases, based on actual file systems (e.g. ext2, FAT32, NTFS, etc.) and actual applications or benchmarks
High level side channel attack modeling and simulation for security-critical systems-on-chips
No full textThe design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side-channel observation. The adoption of high-level countermeasures and the verification of the feasibility of new attacks presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered at high-level simulation in order to evaluate the actual implementation of a cryptographic algorithm, this being software or hardware based. The simulation is performed within a unified tool based on Systeme, which can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation and mixed software-hardware implementations with cycle-accurate resolution. Here, we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and identification of the weaknesses in cryptographic algorithm implementations ("Side Channel Analysis Resistant Design Flow")
Full system emulation of approximate memory platforms with AppropinQuo
Full text linkIn this work we present an emulation framework for hardware platforms provided with approximate memory units, called AppropinQuo. The specific characteristic of AppropinQuo is to reveal the effects, on the hardware platform and on software, of errors introduced by approximate memory circuits and architectures. The emulator allows to execute software code without any modification with respect to the target physical board, since it includes the CPU, the memory hierarchy and the peripherals, capturing as well software-hardware interactions and faults due to approximate memory units. The final scope is reproducing the effects of errors generated by approximate memory circuits, allowing to evaluate the impact (quality degradation) on the output produced by the software. In fact, output quality is related to error rate, but their relationship strongly depends on the application, the implementation and its data representation on physical memory. The idea behind approximate memory circuits and approximate computing in general is to trade off energy consumption at the expense of computational accuracy and degradation of output quality. Memory is accounted for a large part of total power consumption in advanced architectures and it is supposed to increase as new memory hungry applications migrate toward the implementation on embedded systems (embedded machine learning, high definition video codecs, etc.). By relaxing design constraints regarding error probability on bit cells, researchers have proposed techniques that significantly reduce memory energy consumption. These techniques, which can be accounted in the general topic of approximate memory design, are implemented at circuit or architecture level, and are specific to the memory technology (i.e., SRAM or DRAM memories). However, the level of acceptable output degradation is the final metric that must be used to assess if, and to what extent, an approximate memory technique can be introduced. Our emulator allows to run actual applications as on the physical platform, to expose the effects of specific approximate memory circuits and architectures on output quality and to vary their parameters (e.g., error rate, number of affected bits, etc.). By exploring the approximate memory design space and its effects on the output of a software application, it is possible to characterize the application behavior, as a step toward the determination of the trade-off between saved energy and output quality (energy-quality tradeoff)
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