4,425 research outputs found
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
No full textFlexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case
Turbo NOC: a framework for the design of Network-on-Chip-basedturbo decoder architectures
No full textThis paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead
Alessia Pica, Laura Melelli, Martina Burnelli, Maurizio Del Monte, Francesca Vergari and Massimiliano Alvioli
No full textA Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors
No full textReconfigurable embedded systems can take advantage of programmable devices, such as microprocessors and field-programmable gate arrays (FPGAs), to achieve high performance and flexibility. Support to flexibility often comes at the expense of large amounts of nonvolatile memories. Unfortunately, nonvolatile memories, such as multilevel-cell (MLC) NAND flash, exhibit a high raw bit error rate that is mitigated by employing different techniques, including error correcting codes. Recent results show that low-density-parity-check (LDPC) codes are good candidates to improve the reliability of MLC NAND flash memories especially when page size increases. This letter proposes to use a joint source/channel approach, based on a modified arithmetic code and LDPC codes, to achieve both data compression and improved system reliability. The proposed technique is then applied to the configuration data of FPGAs and experimental results show the superior performance of the proposed system with respect to state of the art. Indeed, the proposed system can achieve bit-error-rates as low as about 10e-8 for cell-to-cell coupling strength factors well higher than 1.0
Guest Editorial: Special Issue on Intelligent Embedded Systems Architectures and Applications (INTESA)
No full textIn recent year, embedded systems architectures and applications have gained a lot of interest, especially the possibility to add on-bard intelligence has fostered research in several directions, including not only smart IoT and cyber physical systems, but also hot topics such as accelerating deep learning. This special issue contains four papers dealing with architectures and design methodologies to support embedded intelligence, but also providing best practices and software support.
The paper “A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation”, by Santos et al., aims to focus on Processing-In-Memory (PIM) as a solution for efficiently processing big data. In particular, this work presents a framework to simulate and automatically generate code for IoT PIM-based systems. Moreover, it proposes an high speed and energy efficient architecture for an IoT PIM system, able to compute a real image recognition application.
The paper “Recommender system implementations for embedded collaborative filtering applications”, by Pajuelo-Holguera et al., aims to propose a complete recommender system implemented on reconfigurable hardware with the purpose of testing on-chip, low-energy embedded collaborative filtering applications. The proposed approach solves any prediction problem based on collaborative filtering by using an off-line, highly-portable light computing environment. Moreover, this work exploits a custom, fine-grained parallel circuit for quick matrix multiplication with floating-point numbers.
The paper “SystemC-based Electronic System-Level Design Space Exploration Environment for Dedicated Heterogeneous Multi-Processor Systems”, by Pomante et al., faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multiprocessor architectures. In particular, the work presents a prototype SystemC -based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture.
The paper “A Fast and Scalable Architecture to Run Convolutional Neural Networks in Low Density FPGAs”, by Véstias et al., deals with efficient configurable architectures for Convolutional Neural Networks (CNN) inference targeting any density FPGAs. The architecture exploits fixed-point arithmetic and image batch to reduce computational, memory and memory bandwidth requirements without compromising network accuracy.
In conclusion, this special issue offers some timely contributions to advance the research of intelligent embedded systems by analyzing both architectures and applications. All of four papers are worth reading and will inspire more interesting ideas and research topics.
We sincerely express our gratitude to the Editor-in-Chief of the journal, Prof. Lech Jozwiak for all the valuable advice and constructive comments. We would also like to thank all the reviewers for their hard work on reviewing the papers. Last but not least, we appreciate all the authors who spent time and effort to respond to this call-for-papers. We truly hope that the readers will enjoy and benefit from this special issue
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