41 research outputs found
3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding
No full textABSTRACTMany feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Today's focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands.Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers.Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer.In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.</jats:p
Low Temperature Bonding with Thin Wafers for 3D Integration
No full textThe ITRS roadmap for high-density TSV interconnects specifies maximum layer thicknesses of 5-15 µm in 2013 with a sub-micron layer-to-layer alignment accuracy. For 3D chip stacks with multiple layers it is not only necessary to handle and process such thin layers, but later on these thin layers have to be stacked and bonded. When it comes to wafer bonding for high-density TSV integration, most efforts have been given to developing Cu-Cu thermo-compression bonding and direct oxide bonding. Stacking of thin wafers can be performed either after the thin wafer is debonded or while the thin wafer is still bonded onto a carrier wafer. Bonding of the thin wafer while still mounted to the carrier wafer allows comfortable and safe wafer handling, but adds some complexity to the wafer bonding process.</jats:p
