48 research outputs found

    GaN-based MIS-HEMTs: Impact of cascode-mode high temperature source current stress on NBTI shift

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    This paper reports on the trapping mechanism of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs) designed to work in a cascode configuration. We defined a novel stress protocol (High Temperature, Source Current, HTSC) to investigate the degradation processes induced by semi-on state operation. We compare the results of HTSC with those obtained by the standard HTRB (high temperature reverse bias), with the aim of identifying different impact on the RON variation. While HTRB stress results in a strong negative bias/temperature instability (NBTI), under HTSC conditions no significant Vth shift is observed. This result is ascribed to the fact that under HTSC conditions the gate-source voltage difference is significantly smaller than under HTRB, thus having less impact on Vth stability. The technique described in this paper is useful to test the Vth stability of normally-on devices used in cascode configuration

    NUV-HD SiPMs with metal-filled trenches

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    In this paper we present the performance of a new SiPM that is sensitive to blue light and features narrow metal-filled trenches placed in the area around the single-photon avalanche diodes (SPADs) that allow an almost complete suppression the internal optical crosstalk. In particular, we show the benefits of this technological upgrade in terms of electro-optical SiPM performance when compared to the previous technology which had only a partial optical screening between the SPADs. The most relevant effect is the much higher bias voltage that can be applied to the new device before the noise diverges. This allows to optimize and improve both the photon-detection efficiency and the single-photon time resolution. We also coupled the SiPMs to LYSO scintillators to verify the performance for possible application in Positron-Emission Tomography. Thanks to the better electro-optical features we were able to measure an improved coincidence time resolution. Furthermore, the optimal voltage operation region is substantially larger, making this SiPM more suitable for real system application where thousands of channels have to provide stable and reproducible performance

    Negative bias-induced threshold voltage instability in GaN-on-Si power HEMTs

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    This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on -resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator
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