75 research outputs found
Open Source Remote Diagnostics Platform for Custom Instrumentation in Nuclear Applications
No full textAn open source remote diagnostics platform for custom electronics in experimental acquisition setups has been developed, targeting nuclear and high-energy physics (HEP) applications. We aim at enabling remote access to instrumentation hardware prototypes located in radiation-controlled areas by using existent network infrastructures. The platform relies on two components: a graphical user interface (GUI) developed in GNURadio and a remote hardware bridge (HB). The GUI was designed using the GNURadio’s optimized building blocks, ensuring a fluid visualization of real-time pulse traces and energy spectrum. No third-party libraries are used, turning our solution into an easy drop-in tool for instrumentation diagnostics in HEP and radiation-related experiments. Reliable communication between the remote instrument and the GUI is accomplished using TCP/IP, carried out by the HB in case of remote instruments without network interface. A Raspberry PI Zero-W is tested as the HB to demonstrate the few computational resources required for this end
Study of the Data Exchange between Programmable Logic and Processor System of Zynq-7000 Devices
No full textZynq-7000 devices from Xilinx has gained strong popularity in the last years. Several documents and examples about interfaces usage and how to communicate the programmable logic with the processor are available, but some of them are not properly explained and in particular, the maximum throughput is not clearly specified. With this purpose, in this work a measurement method is presented and applied over the five available interfaces, considering the most used alternatives. Tests were carried on a Zybo board, but the results can be easily used to estimate the performance of others systems setups. Special hardware features and functionality are also discussed, providing a better understanding of system performance. Related papers were studied but none of them presents comparable information as to provide a fair comparison
Design for Portability of Reconfigurable Virtual Instrumentation
No full textA portable architectural design strategy is described for the implementation of reconfigurable virtual instrumentation based on programmable Systems-on-Chip integrating microprocessors and FPGA in the same physical device. The key role is played by a general purpose communication block as a means to efficiently separate the activities carried out in the microprocessor and in the FPGA. Both parts interact according to simple logic protocols by reading and writing data on the common memory resources of the communication block. The architecture of the proposed communication system can be easily implemented in practically any modern programmable System-on-Chip. With the proposed strategy, the porting of embedded software programs and associated FPGA designs among different device families and vendors is facilitated. A structured methodology is proposed for handling complex real-time systems based on these programmable Systems-on-Chip. We described a concrete communication block that has been successfully implemented and utilized for a quick implementation of a data acquisition system based on a Xilinx Zynq-7030 FPGA Mezzanine Card (FMC) and a custom FMC module with an 8-bit 500 MSPS ADC
HyperFPGA: Enhancing Education With Remote Laboratory Access for Heterogeneous Computing on MPSoC-FPGA Technologies
No full textThe HyperFPGA cluster is an experimental platform that aims to provide access to high-performance computing education. Developed at the ICTP's Multidisciplinary laboratory, it features a robust MPSoC-FPGA based remote cluster that can be tailored for students in resource-limited regions. Through an intuitive JupyterHub interface, HyperFPGA provides a rich, hands-on experience in heterogeneous computing, allowing seamless remote interaction with CPU-FPGA systems. By eliminating physical barriers and reducing logistical costs, HyperFPGA democratizes access to advanced computational resources, fostering scalable, collaborative, and impactful learning. Planned future upgrades, such as GPU integration, promise to broaden its reach and reshape the global educational landscape in scientific computing
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
No full textHardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
No full textHardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed.Fil: Molina, Romina. Universidad Nacional de San Luis; ArgentinaFil: Gil Costa, Graciela Verónica. Universidad Nacional de San Luis; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - San Luis; ArgentinaFil: Crespo, Maria Liz. The Abdus Salam; Italia. The Abdus Salam. International Centre for Theoretical Physics; ItaliaFil: Ramponi, Giovanni. Università degli Studi di Trieste; Itali
An End-to-End Workflow to Efficiently Compress and Deploy DNN Classifiers On SoC/FPGA
No full textMachine learning models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high computational complexity. Due to their parallel processing capabilities, reconfigurability, and low power consumption, Systems on Chip based on a Field Programmable Gate Array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a Deep Neural Network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This paper presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization with an ensemble of compression techniques
Muon–Electron Pulse Shape Discrimination for Water Cherenkov Detectors Based on FPGA/SoC
No full textThe distinction of secondary particles in extensive air showers, specifically muons and electrons, is one of the requirements to perform a good measurement of the composition of primary cosmic rays. We describe two methods for pulse shape detection and discrimination of muons and electrons implemented on FPGA. One uses an artificial neural network (ANN) algorithm; the other exploits a correlation approach based on finite impulse response (FIR) filters. The novel hls4ml package is used to build the ANN inference model. Both methods were implemented and tested on Xilinx FPGA System on Chip (SoC) devices: ZU9EG Zynq UltraScale+ and ZC7Z020 Zynq. The data set used for the analysis was captured with a data acquisition system on an experimental site based on a water Cherenkov detector. A comparison of the accuracy of the detection, resources utilization and power consumption of both methods is presented. The results show an overall accuracy on particle discrimination of 96.62% for the ANN and 92.50% for the FIR-based correlation, with execution times of 848 ns and 752 ns, respectively
Gamma/neutron online discrimination based on machine learning with CLYC detectors
No full textAn embedded system for gamma and neutron discrimination in mixed radiation environments is proposed, validated with an off-the-shelf detector consisting of a Cs2LiYCl6:Ce (CLYC) crystal coupled to a silicon photomultiplier (SiPM) cell array. This solution employs a machine learning classification model based on a multilayer perceptron (MLP) running on a commercial Field-Programmable Gate Array (FPGA), providing online single-event identification with 98.2% overall accuracy at rates higher than 200 kilocounts per second. Thermal neutrons and fast neutrons up to 5 MeV can be detected and discriminated from gamma events, even under pile-up scenarios with a dead-time lower than 2.5 μs. The system exhibits excellent size, weight, and power consumption (SWaP) characteristics, packed in a volume smaller than 0.6 liters and weighing less than 0.5 kilograms, while ensuring continuous operation with only 1.5 Watt. These features render our proposal suitable for embedded applications where low SWaP is critical and radiation levels manifest large count rate variability, such as space exploration, portable dosimeters, radiation surveillance on uncrewed aerial vehicles (UAV), and soil moisture monitoring
- …
