253 research outputs found
Synthesis of multiport resistors with piecewise-linear characteristics: a mixed-signal architecture
No full textNon‐linear multiport resistors are the main ingredients in the synthesis of non‐linear circuits. Recently, a particular PWL representation has been proposed as a generic design platform (IEEE Trans. Circuits Syst.‐I 2002; 49:1138–1149). In this paper, we present a mixed‐signal circuit architecture, based on standard modules, that allows the electronic integration of non‐linear multiport resistors using the mentioned PWL structure. The proposed architecture is fully programmable so that the unit can implement any user‐defined non‐linearity. Moreover, it is modular: an increment in the number of input variables can be accommodated through the addition of an equal number of input modules.Fil: Parodi, Mauro. University of Genoa; ItaliaFil: Storace, Marco. University of Genoa; ItaliaFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca; Argentina. Universidad Nacional del Sur; Argentin
Secure communication by hysteresis-based chaotic circuit
No full textA transmitter-receiver system for secure communications is described. Both parts of the circuit are based on a hysteresis chaos generator. The system masks the input by transmitting a chaotic signal and retrieves the informative content in the receiver. A numerical simulation is presented
Digital architectures for the circuit implementation of PWL multi-variate functions: two FPGA implementations
No full textDigital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n=3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function
On the representation of static hysteresis curves by a PWL ladder circuit
No full textSome important features of static hysteretic phenomena can be suitably represented by a recently proposed ladder circuit model. The elementary cell of this ladder is constituted by a linear capacitor and a non-linear resistor with a proper piecewise linear (PWL) characteristic. With respect to the original formulation, the representation capabilities of the model can be improved by introducing proper generalizations. These generalizations concern the definition of the hysteretic (output) variable and the initial states of the circuit capacitors. After introducing these concepts, this paper addresses the determination of the model parameters that give the best fit of the experimental data of a scalar rate-independent hysteresis. The solution of this identification problem is obtained both for a limit cycle and for a cycle together with its first polarization curve
Hardware-in-the-loop simulations of circuit architectures for the computation of exact and approximate explicit MPC control functions
No full textTwo-port ideal power transferitors: a unified introduction to ideal transformer and gyrator
No full textA unified approach to ideal transformer and gyrator is proposed. They are presented as the only two ports belonging to the class of ideal power transferitors, i.e., the only two ports that absorb instantaneous power from one port and supply the same amount of instantaneous power from the other port. By exploiting the transmission matrix, this approach evidences similarities and differences between the two well-known two ports pointing out that other two-port ideal power transferitors cannot exist
Digital architectures implementing piecewise-affine functions: An overview
No full textIn this paper we review and discuss digital circuit architectures implementing piecewise-affine (PWA) functions. These functions are defined over domains that are partitioned (either uniformly or non-uniformly) in polyhedral regions: each PWA function is linear in a polyhedral region. Different solutions, concerning both regular and non-regular domain partitions, are compared in terms of complexity and performances. Measurement results are provided for FPGA implementations. Two examples of control applications are described. On the overall, the goal of this paper is to provide a compact exposition of the state-of-the-art methods for the digital circuit implementation of PWA functions that is accessible to both experts and non-experts
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