3,819 research outputs found
A turbo-decoding message-passing algorithm for sparse parity-check matrix codes
No full textA turbo-decoding message-passing (TDMP) algorithm for sparse parity-check matrix (SPCM) codes such as low-density parity-check, repeat-accumulate, and turbo-like codes is presented. The main advantages of the proposed algorithm over the standard decoding algorithm are 1) its faster convergence speed by a factor of two in terms of decoding iterations, 2) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 3) reduced memory requirements, and 4) reduced decoder complexity. In addition, an efficient algorithm for message computation using simple max operations is also presented. Analysis using EXIT charts shows that the TDMP algorithm offers a better performance-complexity tradeoff when the number of decoding iterations is small, which is attractive for high-speed applications. A parallel version of the TDMP algorithm in conjunction with architecture-aware (AA) SPCM codes, which have embedded structure that enables efficient high-throughput decoder implementation, are presented. Design examples of AA-SPCM codes based on graphs with large girth demonstrate that AA-SPCM codes have very good error-correcting capability using the TDMP algorithm. © 2006 IEEE.BAHL LR, 1974, IEEE T INFORM THEORY, V20, P284, DOI 10.1109-TIT.1974.1055186; Bangerter B., 2003, INTEL TECHNOL J, V7; BENES VE, 1964, ATandT TECH J, V43, P1641; BERROU C, 1993, IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS 93 : TECHNICAL PROGRAM, CONFERENCE RECORD, VOLS 1-3, P1064, DOI 10.1109-ICC.1993.397441; Blanksby AJ, 2002, IEEE J SOLID-ST CIRC, V37, P404, DOI 10.1109-4.987093; Brink S. T., 2001, IEEE T COMMUN, V49, P1727; Divsalar D., 1998, Proceedings. Thiry-Sixth Annual Allerton Conference on Communication, Control, and Computing; FAN J, LDPC EFFICIENT ALTER; Gallager R., 1963, LOW DENSITY PARITY C; Gross WJ, 2001, IEEE T CIRCUITS-II, V48, P904, DOI 10.1109-82.974777; GUILLOUD F, 2004, THESIS ENST PARIS; Hocevar D. E., 2003, P IEEE INT C COMM, P2708; HU XY, 2001, P IEEE GLOB TEL C IE, pE1036; Jin H., 2001, THESIS CALTECH PASAD; Jin H., 2000, P 2 INT S TURB COD R, P1; Kschischang FR, 1998, IEEE J SEL AREA COMM, V16, P219, DOI 10.1109-49.661110; Lan CF, 2004, IEEE T COMMUN, V52, P1092, DOI 10.1109-TCOMM.2004.831406; Lin S., 2004, ERROR CONTROL CODING; LUBOTZKY A, 1988, COMBINATORICA, V8, P261, DOI 10.1007-BF02126799; Mansour M. M., 2002, P INT S LOW POW EL D, P284; MANSOUR MM, 2002, P IEEE GLOB TEL C 20, P1383; Mansor M, 2003, PASOH: ECOLOGY OF A LOWLAND RAIN FOREST IN SOUTHEAST ASIA, P215; MANSOUR MM, 2005, 39 ANN C INF SCI SYS; Mansour MM, 2003, IEEE T VLSI SYST, V11, P976, DOI 10.1109-TVLSI.2003.817545; MANSOUR MM, 2003, P IEEE INT S CIRC SY, V2, P57; MANSOUR MM, 2002, ANN C INF SCI SYST C; MARGULIS GA, 1982, COMBINATORICA, V2, P71, DOI 10.1007-BF02579283; MCLIECE RJ, 1998, IEEE J SEL AREA COMM, V16, P140; Pearl J., 1988, PROBABILISTIC REASON; RASHI Y, EFFICIENT ALTERNATIV; Richardson TJ, 2001, IEEE T INFORM THEORY, V47, P619, DOI 10.1109-18.910578; Rosenthal J., 2000, P 38 ALL C COMM CONT, P248; Roumy A, 2004, IEEE T INFORM THEORY, V50, P1711, DOI 10.1109-TIT.2004.831778; Royle G., CUBIC CAGES; SONG H, 2002, JPN J APPL PHYS, P1749; TANNER RM, 1981, IEEE T INFORM THEORY, V27, P533, DOI 10.1109-TIT.1981.1056404; Tanner R. M., 1999, P 37 ALL C COMM CONT; TANNER RM, 2001, P INT S COMM THEOR A, P1; Tanner RM, 2004, IEEE T INFORM THEORY, V50, P2966, DOI 10.1109-TIT.2004.838370; TUCHLER M, 2002, C INF SCI SYST PRINC; Vasic B, 2003, J LIGHTWAVE TECHNOL, V21, P438, DOI 10.1109-JLT.2003.808769; Yang M, 2004, IEEE T COMMUN, V52, P564, DOI 10.1109-TCOMM.2004.826367; YEO E, 2001, P IEEE GLOBECOM, P3019; Zhang JT, 2005, IEEE T COMMUN, V53, P209, DOI 10.1109-TCOMM.2004.84198252453
A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes
No full textA new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic-scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm 2 programmable decoder core for a rate-1-2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power. © 2005 Springer Science + Business Media, Inc.BAHL LR, 1974, IEEE T INFORM THEORY, V20, P284, DOI 10.1109-TIT.1974.1055186; BERROU C, 1993, IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS 93 : TECHNICAL PROGRAM, CONFERENCE RECORD, VOLS 1-3, P1064, DOI 10.1109-ICC.1993.397441; Gallager R., 1963, LOW DENSITY PARITY C; HU XY, 2001, GLOBECOM 2001, V2, P1036; Mansour M. M., 2002, IEEE Workshop on Signal Processing Systems (SPIS'02) (Cat. No.02TH8638), DOI 10.1109-SIPS.2002.1049702; Mansour M. M., 2002, P INT S LOW POW EL D, P284; MANSOUR MM, 2002, P IEEE GLOB TEL C 20, P1383; MANSOUR MM, 2003, THESIS U ILLINOIS UR; Mansour MM, 2003, IEEE T VLSI SYST, V11, P976, DOI 10.1109-TVLSI.2003.817545; Mansour MM, 2003, IEEE COMP SOC ANN, P62, DOI 10.1109-ISVLSI.2003.1183354; MANSOUR MM, 2002, C INF SCI SYST PRINC; ROWLAND C, 2001, P 2001 IEEE INT C CI, P742; Wiberg N., 1996, THESIS LINKOPING U S; Yeo E, 2001, IEEE T MAGN, V37, P7480
A reconfigurable TDMP decoder for raptor codes
No full textA Raptor code is a concatenation of a fixed rate precode and a Luby-Transform (LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: (1) applying systematic permutations on the source matrix of the Raptor code, (2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of rowsplitting scenarios, and (3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT- and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb-s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm 2. © Springer Science+Business Media, LLC 2012.Elias P, 1955, 3 LOND S, P61; Etesami O, 2006, IEEE T INFORM THEORY, V52, P2033, DOI 10.1109-TIT.2006.872855; Fossorier MPC, 1999, IEEE T COMMUN, V47, P673, DOI 10.1109-26.768759; Gallager R., 1963, LOW DENSITY PARITY C; Kai Zhang X. H., 2009, IEEE T VERY LARGE SC, V27, P985; Luby M, 2002, ANN IEEE SYMP FOUND, P271; Mansour MA, 2006, IEEE T SIGNAL PROCES, V54, P4376, DOI 10.1109-TSP.2006.880240; Mansour MM, 2003, IEEE T VLSI SYST, V11, P976, DOI 10.1109-TVLSI.2003.817545; Palanki R., 2004, Proceedings. 2004 IEEE International Symposium on Information Theory (IEEE Cat. No.04CH37522); Shokrollahi A, 2006, IEEE T INFORM THEORY, V52, P2551, DOI 10.1109-TIT.2006.874390; TANNER RM, 1981, IEEE T INFORM THEORY, V27, P533, DOI 10.1109-TIT.1981.1056404; Xiang B, 2010, IEEE T VLSI SYST, V18, P1447, DOI 10.1109-TVLSI.2009.2025169; Zeineddine H, 2011, IEEE T SIGNAL PROCES, V59, P2943, DOI 10.1109-TSP.2011.21146550
A hardware-efficient algorithm for real-time computation of zadoff-chu sequences
No full textA hardware-efficient algorithm and architecture for computing Zadoff-Chu (ZC) sequence elements on-line using the CORDIC algorithm are proposed. Zadoff-Chu sequences possess good correlation properties that are essential in a variety of engineering applications, such as establishing timing synchronization between a mobile terminal and a base station in the emerging 3GPP long-term evolution (LTE) physical layer standard for cellular communications. The proposed algorithm computes ZC-sequence elements both in time domain and frequency domain using a simple duality relationship. Algorithm transforms are employed to compute the elements recursively and eliminate the need for multipliers with non-constant terms. A reconfigurable hardware architecture was implemented and applied in a searcher block for detecting the physical random access channel (PRACH) in LTE. The PRACH provides a mechanism for a mobile to establish initial access along with uplink synchronization by transmitting a preamble that is constructed from ZC sequences. The proposed architecture is capable of generating these preambles on the fly with high accuracy, eliminating the need for storing a large number of long complex-valued ZC sequence elements. Simulation results demonstrate that the proposed architecture is capable of achieving detection error rates for LTE PRACH that are close to ideal rates achieved using floating point precision. (The work has been presented in part in Mansour (2009).). © Springer Science+Business Media New York 2012
Pruned bit-reversal permutations: Mathematical characterization, fast algorithms and architectures
No full textA mathematical characterization of serially pruned permutations (SPPs) employed in variable-length permuters and their associated fast pruning algorithms and architectures are proposed. Permuters are used in many signal processing systems for shuffling data and in communication systems as an adjunct to coding for error correction. Typically, only a small set of discrete permuter lengths are supported. Serial pruning is a simple technique to alter the length of a permutation to support a wider range of lengths, but results in a serial processing bottleneck. In this paper, parallelizing SPPs is formulated in terms of recursively computing sums involving integer floor functions using integer operations, in a fashion analogous to evaluating Dedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) is presented, and closed-form expressions for BRP statistics including descents-ascents, major index, excedances-descedances, inversions, and serial correlations are derived. It is shown that BRP sequences have weak correlation properties. Moreover, a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers is proposed. Using this statistic, a recursive algorithm that computes the minimum inliers count of a pruned BR interleaver (PBRI) in logarithmic time is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers, as well as applications to pruned fast Fourier transforms and LTE turbo interleavers, are also presented. Moreover, hardware-efficient architectures for the proposed algorithms are developed. Simulation results of interleavers employed in modern communication standards demonstrate three to four orders of magnitude improvement in interleaving time compared to existing approaches. © 1991-2012 IEEE.3GPP, 2008, 36212 3GPP TS; [Anonymous], 2008, 80220 IEEE; [Anonymous], 2009, 80216 IEEE; [Anonymous], 2011, 302755 ETSI EN; [Anonymous], 2009, 80211N IEEE; BERROU C, 2004, P IEEE INT C COMM IC, V1, P341; Berrou C., 1993, P IEEE INT C COMM IC, V2, P1064, DOI 10.1109-ICC.1993.397441; BINGHAM JAC, 1990, IEEE COMMUN MAG, V28, P5, DOI 10.1109-35.54342; BISWAS A, 1991, IEEE T SIGNAL PROCES, V39, P1415, DOI 10.1109-78.136547; BURRUS CS, 1988, IEEE T ACOUST SPEECH, V36, P1086, DOI 10.1109-29.1631; Chang GJ, 1999, NETWORKS, V33, P261, DOI 10.1002-(SICI)1097-0037(199907)33:4261::AID-NET33.0.CO;2-Q; Clarke RJ, 1997, ADV APPL MATH, V18, P237, DOI 10.1006-aama.1996.0506; COOLEY JW, 1965, MATH COMPUT, V19, P297, DOI 10.2307-2003354; Crozier S, 2001, IEEE VTS VEH TECHNOL, P2394, DOI 10.1109-VTC.2001.957178; DIETER U, 1971, NUMER MATH, V17, P101, DOI 10.1007-BF01406000; Dinoi L, 2005, IEEE T WIREL COMMUN, V4, P2540, DOI 10.1109-TWC.2005.853836; Divsalar D, 1995, MILCOM 95 - CONFERENCE RECORD, VOLS 1-3, P279, DOI 10.1109-MILCOM.1995.483313; Dolinar S., 1995, 42122 JPL TDA; Drouiche K, 2001, IEEE T SIGNAL PROCES, V49, P251, DOI 10.1109-78.890370; Elster A., 1989, P IEEE C AC SPEECH S, V2, P1099; Eroz M, 1999, IEEE VTS VEH TECHNOL, P1669, DOI 10.1109-VETEC.1999.780687; EVANS DMW, 1987, IEEE T ACOUST SPEECH, V35, P1120, DOI 10.1109-TASSP.1987.1165252; Ferrari M, 2002, 2002 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-5, CONFERENCE PROCEEDINGS, P1711, DOI 10.1109-ICC.2002.997141; FORNEY GD, 1971, IEEE T COMMUN TECHN, VCO19, P772, DOI 10.1109-TCOM.1971.1090719; Gallager R., 1963, LOW DENSITY PARITY C; Garello R, 2001, IEEE T COMMUN, V49, P793, DOI 10.1109-26.923803; He SS, 1996, IEEE SIGNAL PROC LET, V3, P173; HOLM S, 1987, IEEE T ACOUST SPEECH, V35, P1776, DOI 10.1109-TASSP.1987.1165102; Hu Z, 2005, IEEE T SIGNAL PROCES, V53, P274, DOI 10.1109-TSP.2004.838925; JEONG JC, 1992, IEEE T SIGNAL PROCES, V40, P1091, DOI 10.1109-78.134472; Kim K, 1999, IPPS PROC, P268; Knuth D.E., 1998, ART COMPUTER PROGRAM, VII; Lee R., 2004, P INT C INF TECHN CO, V2, P569; MacMahon P. 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A Parallel pruned bit-reversal interleaver
No full textA parallel algorithm and architecture for pruned bit-reversal interleaving (PBRI) are proposed. For a pruned interleaver of size N with mother interleaver size M=2 n ≥ N, the proposed algorithm interleaves any number x ε [0, N- 1] in at most n- 1 steps, as opposed to x steps using existing PBRI algorithms. A parallel architecture of the proposed algorithm employing simple logic gates and having a short critical path delay is presented. The proposed architecture is valuable in reducing (de-)interleaving latency in emerging wireless standards that employ PBRI channel (de-)interleaving in their PHY layer such as the 3GPP2 Ultra Mobile Broadband standard. © 2006 IEEE.DANESHGARAN F, 2004, IEEE T INFORM THEORY, V50, P445; Dobkin R, 2005, IEEE T VLSI SYST, V13, P427, DOI 10.1109-TVLSI.2004.842916; EROZ M, 1999, P IEEE 49 VEH TECHN, V2, P1669; Giulietti A, 2002, ELECTRON LETT, V38, P232, DOI 10.1049-el:20020148; Lin S., 2004, ERROR CONTROL CODING; Prado J, 2004, IEEE SIGNAL PROC LET, V11, P933, DOI 10.1109-LSP.2004.838211; Shao J., 2005, ACM INT C P SERIES, V136, P62; Shin MC, 2003, IEEE COMMUN LETT, V7, P210, DOI 10.1109-LCOMM.2003.812176; Tarable A, 2004, IEEE T INFORM THEORY, V50, P2002, DOI 10.1109-TIT.2004.833353; THUL MJ, 2002, P 9 INT C EL CIRC SY, V3, P1099; WALKER JS, 1990, IEEE T ACOUST SPEECH, V38, P1472, DOI 10.1109-29.57586; 2007, PHYS LAYER STANDARD33
Fast pruned interleaving
No full textIn this paper, computationally efficient schemes for enumerating the so-called inliers of a wide range of permutations employed in pruned variable-size (turbo) interleavers are proposed. The objective is to accelerate pruned interleaving time in turbo codes by computing a statistic known as the pruning gap that enables determining a permuted address under pruning without serially permuting all its predecessors. It is shown that for any linear or quadratic permutation, including variations such as dithered relative prime or almost regular, the pruning gap can be computed in logarithmic time. Moreover, it is shown that Dedekind sums form efficient building blocks for enumerating inliers of the widely adopted polynomial-based permutations. An efficient algorithm for computing such sums in vector form using integer operations is presented. The results are extended to 2D and higher dimensional interleavers that combine multiple permutations along all dimensions, and closed-form expressions for inliers are derived. It is shown that the inliers statistic is a linear combination of the constituent permutation inliers. A lower bound on the minimum spread of serially pruned interleavers using the inliers statistic is also derived. Moreover, it is shown that serially pruned interleavers inherit the content-free property of the mother interleaver, and hence they are parallelizable. Simulation results of practical pruned turbo interleavers demonstrate a speedup improvement of several orders of magnitude compared to serial interleaving. © 1972-2012 IEEE.BERLEKAMP ER, 1978, IEEE T INFORM THEORY, V24, P384, DOI 10.1109-TIT.1978.1055873; Blahut R. E., 1983, THEORY PRACTICE ERRO; Chang YS, 2003, IEEE T COMMUN, V51, P1463, DOI 10.1109-TCOMM.2003.816994; CHASE D, 1972, IEEE T INFORM THEORY, V18, P170, DOI 10.1109-TIT.1972.1054746; CHEN X, 1994, IEE P-COMPUT DIG T, V141, P253, DOI 10.1049-ip-cdt:19941294; CHEN XM, 1994, IEEE T INFORM THEORY, V40, P1654; Chen YH, 2007, J INF SCI ENG, V23, P127; Chertkov M., P 2007 IEEE INT S IN, P1546; CHIEN RT, 1964, IEEE T INFORM THEORY, V10, P357, DOI 10.1109-TIT.1964.1053699; ELIA M, 1987, IEEE T INFORM THEORY, V33, P150, DOI 10.1109-TIT.1987.1057262; Feldman J, 2005, IEEE T INFORM THEORY, V51, P954, DOI 10.1109-TIT.2004.842696; HAMMING RW, 1950, ATandT TECH J, V29, P147; He RH, 2001, IEEE T INFORM THEORY, V47, P1181; Lin S., 2004, ERROR CONTROL CODING; Lin T. C., P 2009 IEEE PIMRC, P1824; Lin TC, 2011, IEEE COMMUN LETT, V15, P226, DOI 10.1109-LCOMM.2010.121310.101225; Miwa M, 2009, IEEE J SEL AREA COMM, V27, P1005, DOI 10.1109-JSAC.2009.090818; Prange E., 1958, TN156 AIR FORC CAMBR; REED IS, 1990, IEE PROC-E, V137, P202; Reed I. S., 1999, ERROR CONTROL CODING; REED IS, 1991, IEE PROC-E, V138, P295; REED IS, 1992, IEEE T INFORM THEORY, V38, P974, DOI 10.1109-18.135639; REED IS, 1990, IEEE T INFORM THEORY, V36, P876, DOI 10.1109-18.53750; Szabo Z., 2003, AN ST U OVIDIUS CONS, V11, P155; Taghavi MH, 2008, IEEE T INFORM THEORY, V54, P5396, DOI 10.1109-TIT.2008.2006384; TAIPALE DJ, 1991, IEEE T INFORM THEORY, V37, P167, DOI 10.1109-18.61132; Tanatmis A, 2010, IEEE T INFORM THEORY, V56, P3277, DOI 10.1109-TIT.2010.2048489; Truong TK, 2005, IEEE T COMMUN, V53, P749, DOI 10.1109-TCOMM.2005.847147; Truong TK, 2008, IEEE T INFORM THEORY, V54, P5005, DOI 10.1109-TIT.2008.929956; Yang K, 2008, IEEE T INFORM THEORY, V54, P1061, DOI 10.1109-TIT.2007.915712; Youzhi X., 1991, P I ELECTR ENG, V138, P138; Zhang X., IEEE T INF THEORY0
High-performance decoders for regular and irregular repeat-accumulate codes
No full textThis paper investigates high-performance decoder design for regular and irregular repeat-accumulate (RA) codes of large block length. In order to achieve throughputs and bit-error rate performance that are inline with future trends in high-speed communications, high-throughput and low-power decoders of low complexity are needed. To meet such conflicting requirements for long codes, the concept of architecture-aware RA (AARA) code design is proposed. AARA code design decouples the complexity of the decoder from the code structure by inducing structural regularity features that are amenable to efficient and scalable decoder implementations. Design methods of AARA codes with structured permuters for which an iterative decoding algorithm performs well under message-passing are analogous to those for AA LDPC codes. Algorithmic and architectural optimizations that address the latency, memory overhead, and complexity problems typical of iterative decoders for long RA codes are investigated, and a staggered decoding schedule is introduced. AARA decoders using the proposed schedule have substantial advantage over serial and parallel RA decoders. © 2004 IEEE.
High-performance decoders for regular and irregular repeat-accumulate codes
No full textThis paper investigates high-performance decoder design for regular and irregular repeat-accumulate (RA) codes of large block length. In order to achieve throughputs and bit-error rate performance that are inline with future trends in high-speed communications, high-throughput and low-power decoders of low complexity are needed. To meet such conflicting requirements for long codes, the concept of architecture-aware RA (AARA) code design is proposed. AARA code design decouples the complexity of the decoder from the code structure by inducing structural regularity features that are amenable to efficient and scalable decoder implementations. Design methods of AARA codes with structured permuters for which an iterative decoding algorithm performs well under message-passing are analogous to those for AA LDPC codes. Algorithmic and architectural optimizations that address the latency, memory overhead, and complexity problems typical of iterative decoders for long RA codes are investigated, and a staggered decoding schedule is introduced. AARA decoders using the proposed schedule have substantial advantage over serial and parallel RA decoders. © 2004 IEEE.
On the contention-free and spread characteristics of serially-pruned interleavers
No full textSerial pruning of turbo interleavers have been proposed in the literature as a simple scheme to provide more flexible codeword lengths. In this paper, we prove two important attributes about serially pruned interleavers. First, we show that serially pruned interleavers inherit the content-free property of their mother interleaver, and hence they remain parallelizable. An example serially-pruned QPP LTE interleaver is parallelized. Second, the minimum spread factor of a serially-pruned interleaver closely matches the spread factor of its mother interleaver for small pruning gaps with minimal impact on BER performance, and degrades gracefully with the pruning length. Simulation results of practical pruned LTE turbo interleavers demonstrate the graceful degradation of spread characteristics and BER performance of serially pruned interleavers. © 2013 IEEE
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