101 research outputs found
Challenges and Opportunities in Exascale-Computing Interconnects
No full textKeynote Talk, given by Manolis Katevenis and Nikolaos Chrysos, at the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS 2016), held in conjunction with the HiPEAC 2016 Conference, Prague, Czech Republic, 18 January 2016
Presentation of the ExaNeSt project at the European HPC Summit Week 2016
No full textExaNeSt in 8 slides: Presentation of the ExaNeSt project at the European HPC Summit Week 2016; Prague, Czech Republic, 10 May 2016.www.exanest.e
Telegraphos: High-Speed Communications Architecture for Parallel and Distributed Computer Systems
No full textABSTRACT: Telegraphos is an R&D project in computer communication. It useshardware switches for building high-speed multiprocessor or local area networks; preventive flow control eliminates packet dropping, and dedicated buffers per VCoffer congestion tolerance. The network interfaces have low complexity because they never need to retransmit packets, and because they use a single address space archi-tecture. Message passing is done with the remote write primitive; overhead is minimized because address translation also performs message protection. Other remotememory operations, including eager updates and hardware monitors, provide effective and low-cost support for virtual shared memory. Telegraphos I, our first proto-type, is currently being built
Proceedings of the Third International Conference on High-Performance Embedded Architectures and Compilers
No full text
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
No full text<p>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.</p>
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
No full textAbstract – Quality-of-Service (QoS) guarantees in networks are increasingly based on per-flow queueing and sophisticated scheduling. Most advanced scheduling algorithms rely on a common computational primitive: priority queues. Large priority queues are built using calendar queue or heap data structures. To support advanced scheduling at OC-192 (10 Gbps) rates and above, pipelined management of the priority queue is needed. We present a pipelined heap manager that we have designed as a core integratable into ASIC’s, in synthesizable Verilog form. We discuss how to use it in switches and routers, its advantages over calendar queues, and we present cost-performance tradeoffs. Our design can be configured to any heap size. We have verified and synthesized our design and present cost and performance analysis information
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