297 research outputs found
Is the incidence of dementia declining?
No full textAction on preventative health could lower the risk of dementia for future generations, argues this report.
Executive summary
The world-wide projections of the prevalence of dementia in the coming decades have been a source of great concern to health systems and societies around the world. The World Alzheimer Report 2010 estimated that there were 36 million people with dementia in 2010, with an expected doubling every 20 years to nearly 115 million in 2050. These sobering figures are based on assumptions that the age-adjusted prevalence of dementia would remain constant and the population would continue to age at the current rate.
The assumption that the incidence of dementia will remain stable is now being put into question. There is emerging evidence to suggest that the incidence of dementia in older individuals may be declining. It appears that this change may be recent and has possibly occurred only in the last one to two decades. It may also be restricted so far to high income countries, although data from low and middle income countries are lacking.
The reasons for this change are not understood, but education, more stimulating environments and better control of vascular risk factors may have contributed. The data are still preliminary and more studies are needed to establish the extent of this change and understand its causes. It should be noted that the decline is not large enough to offset the increase in prevalence of dementia due to the ageing of the population and therefore investment and efforts to develop better treatments and care for people with dementia need to continue.
The fact that dementia rates are malleable is an encouraging finding but the reduction cannot be taken for granted as gains in population health can easily be lost if societies do not remain vigilant and continually proactive. These preliminary findings provide a strong argument for large scale Government investment in dementia-prevention strategies, which should start from early life
Sachdev–Ye–Kitaev model as Liouville quantum mechanics
No full textAbstractWe show that the proper inclusion of soft reparameterization modes in the Sachdev–Ye–Kitaev model of N randomly interacting Majorana fermions reduces its long-time behavior to that of Liouville quantum mechanics. As a result, all zero temperature correlation functions decay with the universal exponent ∝τ−3/2 for times larger than the inverse single particle level spacing τ≫NlnN. In the particular case of the single particle Green function this behavior is manifestation of the zero-bias anomaly, or scaling in energy as ϵ1/2. We also present exact diagonalization study supporting our conclusions
Modified Differential Cascode Voltage Switch Logic Optimized for Sub-threshold Voltage Operation
No full textUltra-low sub-threshold voltage research has become increasingly important with the recent shift in consumer electronics towards low power designs for mobile, wearable, and implantable technologies. These applications are able to trade-off speed for reduced power consumption and reduced minimum operating voltage. This thesis studies circuit design solutions that focus on achieving the lowest minimum operating voltages. These applications are likely to be ones where the supply voltage may come from energy harvesting sources that are only able to source ultra-low voltages. The logic circuit presented in this thesis is a modified implementation of differential cascade voltage switch logic (DCVSL). Differential logic has improved ultra-low voltage performance over static CMOS logic and the modification to DCVSL offers a logic structure that can implement multi-input AND/NAND and OR/NOR gates while maintaining a stack height of one. This logic circuit is referred in this thesis as MOD-DCVSL. The modification requires the use of capacitive boosting to allow for normal logic operation. The results of this thesis show that differential logic styles are able to perform at lower minimum operating voltages compared to static CMOS logic styles but at the cost of larger delay and power compared to static CMOS. On average the differential implementations could operate at a minimum supply voltage 5mV lower than CMOS for two input implementations and 10mV lower for three input implementations. The delay of differential implementations was approximately double for both two and three input implementations. The power of the differential implementations are approximately 20% higher than static CMOS for two input implementations but this gap is narrowed to approximately 10% for three input implementations, here the lower minimum operating voltages allowed for decreased power consumption. Due to the consistently lower delay, static CMOS had a lower power delay product than the differential logic. When comparing only the differential logic, MOD-DCVSL offered negligible difference for two input implementations but was able to improve delay by 7% and power by 11% in the three input implementations
Secure and Unclonable Integrated Circuits
No full textSemiconductor manufacturing is increasingly reliant in offshore foundries, which has raised concerns with counterfeiting, piracy, and unauthorized overproduction by the contract foundry. The recent shortage of semiconductors has aggravated such problems, with the electronic components market being flooded by recycled, remarked, or even out-of-spec, and defective parts. Moreover, modern internet connected applications require mechanisms that enable secure communication, which must be protected by security countermeasures to mitigate various types of attacks. In this thesis, we describe techniques to aid counterfeit prevention, and mitigate secret extraction attacks that exploit power consumption information.
Counterfeit prevention requires simple and trustworthy identification. Physical unclonable functions (PUFs) harvest process variation to create a unique and unclonable digital fingerprint of an IC. However, learning attacks can model the PUF behavior, invalidating its unclonability claims. In this thesis, we research circuits and architectures to make PUFs more resilient to learning attacks. First, we propose the concept of non-monotonic response quantization, where responses not always encode the best performing circuit structure. Then, we explore the design space of PUF compositions, assessing the trade-off between stability and resilience to learning attacks. Finally, we introduce a lightweight key based challenge obfuscation technique that uses a chip unique secret to construct PUFs which are more resilient to learning attacks.
Modern internet protocols demand message integrity, confidentiality, and (often) non-repudiation. Adding support for such mechanisms requires on-chip storage of a secret key. Even if the key is produced by a PUF, it will be subject to key extraction attacks that use power consumption information. Secure integrated circuits must address power analysis attacks with appropriate countermeasures. Traditional mitigation techniques have limited scope of protection, and impose several restrictions on how sensitive data must be manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data in the clear, where all values are protected using Boolean masking and differential domino logic. Software can run with little to no countermeasures, reducing code size and performance overheads. Our methodology is fully automated and can be applied to designs of arbitrary size or complexity. We also provide details on other key components such as clock randomizer, memory protection, and random number generator
Realization of Non-Volatile Memory in Amorphous Silicon Thin-Film Transistors
No full textThe integration of memory circuits in thin-film transistors (TFTs) is essential to extend the functionalities of large-area applications such as flat-panel displays, imagers etc. Intensive research is being conducted with the goal of producing high-performance memory devices for active-matrix backplane electronics. For example, a memory in a pixel circuit has the potential to reduce the refresh rate for display applications. This eventually leads to reduced power consumption which is vital for producing low-power displays. In addition, memory in pixel circuits can improve the fill factor of the display by its ability to hold the data without the need for a storage capacitor. Prior work has reported various TFT structures justifying the performance of the devices especially on their behavior under floating conditions. This work investigates the effect of continuous read cycles on the stability of low-temperature hydrogenated amorphous silicon (a-Si:H) memory TFTs prepared using the industrial standard back-channel etched (BCE) TFT process, as the topic yet to be explored systematically.
An engineered charge-trapping interface between the gate dielectric and the channel layer is fabricated to realize non-volatile memory. The performance of the devices was initially measured by comparing the transfer characteristics of the memory TFTs with conventional a-Si:H TFTs. The stability of the memory devices was measured under different stress conditions by varying the gate voltage and stress time. An emphasis was placed on the stability of the memory devices under floating and persistent read cycles as followed in display applications. The drain current was measured over various intervals of time for ~60 days to track the degradation of the devices. The reliability of the memory devices was also measured.
From the analysis of the results, the charge-trapping memory TFTs demonstrated good stability, large memory window, and better endurance. The charge retention of the devices under floating conditions was extrapolated and it showed a lifetime of ~10 years. However, the charge retention of the memory TFTs exhibited a 50% decrease in lifetime under realistic persistent read bias conditions (~5 years). This is possibly due to the instability of a-Si:H devices. This lifetime is subjected to change under different read voltage. Hence, the lifetime under continuous read cycles is extremely important to provide boundaries for expected memory lifetimes under normal display operating conditions
Design and analysis of high performance low noise oscillators and phase lock loops
No full textThe design and implementation of high purity, high speed and power efficient clock generation Integrated Circuits continue to be one the greatest challenges facing IC designers today. In order to address this challenge, this thesis considers the modeling and design of two fundamental clock generation circuits – the VCO and PLL.An improved ring oscillator topology is proposed which has the advantage of an ultra wide tuning range. A novel noise aware ring oscillator model is also proposed which links the noise performance of the oscillator to its transistor dimensions giving insight to the design procedure. The use of this VCO model in a noise-aware PLL model allows the trade-off between noise performance and the loop bandwidth to be quantified accurately. From further analysis of the proposed PLL model, a novel PLL structure has been designed which is extremely successful at reference spur suppression.Simulation results based on the proposed model and foundry BSIM3v3 models are provided for all the VCO and PLL designs. To validate the proposed VCO topology and VCO model, two prototype chips have been fabricated and measured results show close agreement with theoretical analysis and simulatio
Circuit Design of SRAM Physically Unclonable Functions
No full textA Physically Unclonable Function (PUF) is an entity that reliably provides a unique response to a given challenge and cannot be easily duplicated physically. PUFs are an alternative to using non-volatile memory (NVM) for secure key storage. NVMs are susceptible to reverse engineering and side channel attacks that can extract sensitive data. PUFs take advantage of random physical variations that are introduced during manufacturing. PUFs can be used to create digital fingerprints as secret keys for cryptographic algorithms or for device authentication. SRAM PUFs, in particular, are of great interest due to their omnipresence in electronics. One of the weaknesses of SRAM PUFs is their reliability as noise and other environmental effects reduce the reproducibility of the PUF.
This thesis provides an in depth analysis of the 6T SRAM PUF and 8T soft error robust SRAM PUF at the transistor level and provides a methodology to design a reliable PUF. We hypothesize that the VGS of pull up and pull down transistors during the power up phase affects PUF reliability. Transistors with a larger VGS have higher drive strength and more influence over the start-up value of the PUF. Changing the sizing ratio of PMOS to NMOS devices changes the VGS. Nominal simulations recorded VGS in relation to the VDD ramp-up to predict which devices have a higher influence on start up values.
Two types of PUF schemes: VDD manipulation and GND manipulation are simulated. Monte Carlo simulations are performed within the Cadence Virtuoso environment using TSMC general purpose CMOS kit. The reliability metric is called the assured response which is the number of Monte Carlo samples that show a consistent response over 100 power ups.
The results from VGS dependency analysis and isolated mismatch show a clear trend between VGS and the type of device that determines PUF reliability. Devices with higher VGS during VGS dependency analysis show a larger drop in assured response when their mismatch is disabled in the isolated mismatch simulation. Sizing sweeps show that skewed designs have higher assured response than less skewed designs. This is because smaller transistors have poor matching properties and relatively higher VGS which contribute to improved reliability. VDD manipulation and GND manipulation showed similar levels of reliability while 6T performed better than 8T. In an effort to improve the 8T PUF, a split VDD scheme is proposed which introduces a delay between two VDD signals in the cell. This shows a 3% improvement over a skewed 6T VDD design which was previously the best performer
An Energy-Efficient System with Timing-Reliable Error-Detection Sequentials
No full textA new type of energy-efficient digital system that integrate EDS and DVS circuits has been developed. In these systems, EDS-monitored paths convert the PVT variations into timing variations. Nevertheless, the conversion can suffer from the reliability issue (extrinsic EDS-reliability). EDS circuits detect the unfavorable timing variations (so called ``error'') and guide DVS circuits to adjust the operating voltage to a proper lower level to save the energy. However, the error detection is generally susceptible to the metastability problem (intrinsic EDS-reliability) due to the synchronizer in EDS circuits. The MTBF due to metastability is exponentially related to the synchronizer delay.
This dissertation proposes a new EDS circuit deployment strategy to enhance the extrinsic EDS-reliability. This strategy requires neither buffer insertion nor an extra clock and is applicable for FPGA implementations. An FPGA-based Discrete Cosine Transform with EDS and DVS circuits deployed in this fashion demonstrates up to 16.5\% energy savings over a conventional design at equivalent frequency setting and image quality, with a 0.8\% logic element and 3.5\% maximum frequency penalties.
VBSs are proposed to improve the synchronizer delay under single low-voltage supply environments. A VBS consists of a Jamb latch and a switched-capacitor-based charge pump that provides a voltage boost to the Jamb Latch to speed up the metastability resolution. The charge pump can be either CVBS or MVBS. A new methodology for extracting the metastability parameters of synchronizers under changing biasing currents is proposed. For a 1-year MTBF specification, MVBS and CVBS show 2.0 to 2.7 and 5.1 to 9.8 times the delay improvement over the basic Jamb latch, respectively, without large power consumption. Optimization techniques including transistor sizing, FBB and dynamic implementation are further applied. For a common MTBF specification at typical PVT conditions, the optimized MVBS and CVBS show 2.97 to 7.57 and 4.14 to 8.13 times the delay improvement over the basic Jamb latch, respectively. In post-Layout simulations, MVBS and CVBS are 1.84 and 2.63 times faster than the basic Jamb latch, respectively
Low-power and Radiation Hardened TSPC Registers
No full textBattery-operated systems require power and energy-efficient circuits to extend their battery life. Flip-flops (FFs) are a basic component of digital circuits, and their power consumption and speed significantly impact the overall performance of a digital system. A clock network in a complex System-on-Chip (SoC) consumes a substantial amount of power. Additionally, often pipelines are used to enhance the system throughput, which puts additional burden on the clock network. Arguably, a flip-flop with fewer clock transistors will reduce its power burden on the clock network. This research proposes three very low-power Single-edge Triggered (SET) True Single-phase Clock (TSPC) FFs with only two and three clock transistors. Moreover, a scan-chain of 256 FFs and AES-128 encryption engine were designed as a benchmark to further investigate the power savings of the proposed FFs. Additionally, we have also designed three very low-power Dual-edge Triggered (DET) latch-multiplexer
type TSPC FFs with only eight and ten clock transistors to sample the data at both positive and negative clock edges.
Furthermore, high-performance computations in Integrated Circuits (ICs) are increasingly needed for space and safety-critical applications. ICs are subjected to high-energy ionizing particles in the radiant space environment, which will cause the device performance to degrade or even fail. A Single Event Upset (SEU) occurs in the logic circuit when an ion strikes a device’s sensitive node, changing the output from 0 to 1 or from 1 to 0. In radiant applications, ICs contain storage cells like FFs, latches, or Static Random Access Memories (SRAM), and always experience SEU. Although package and process engineering can minimize alpha particles, cosmic neutrons cannot be physically blocked. Therefore, for high reliability systems, soft error tolerant circuit designs are crucial. Traditional Radiation Hardened By Design (RHBD) techniques have some trade-offs between area, speed, power, and energy consumption. Thus, new designs are required to reduce these penalties. This research proposes two high-performance, low-power, low-energy, and low-area RHBD TSPC FFs with only four and five clock transistors suitable for space and safety-critical applications
Low-Power and High-Performance Drivers for OLEDoS Microdisplays
No full textThe rapid growth of the microdisplay market, driven by the demand for smartwatches, head-mounted displays in Virtual Reality (VR) and Augmented Reality (AR), and other portable devices, has presented a need to enhance their energy efficiency. This thesis focuses on reducing the power and energy consumption of microdisplays while maintaining display luminance, and image quality; and enhancing key features such as resolution, refresh rate, and color depth.
First, a novel driving method and pixel circuit are proposed that reduces the number of subframes in a digitally-driven display. The dual-driver method offers flexibility in different design modes, allowing for the enhancement of various display characteristics. In the low-power mode, the operating frequency is reduced, resulting in decreased dynamic power consumption by the drivers. Experimental results on a proof-of-concept array fabricated using TSMC 65 nm technology demonstrate a significant 39% reduction in power consumption compared to a conventional array. Furthermore, designing the display in other modes yields remarkable improvements, with up to 8.5 times enhancement in refresh rate or resolution. In addition, the high color depth mode presents an opportunity to increase color depth from 8 bits to 14 bits, enhancing the visual experience.
Additionally, this thesis investigates power reduction techniques specific to row drivers in microdisplays. Circuit techniques are proposed to recycle energy in the row driver, thereby reducing dynamic power consumption. Measurement results on proof-of-concept arrays implemented in TSMC 65 nm technology reveal substantial reductions of up to 30% in the power consumption of the row driver using different energy recycling techniques. Applying these techniques led to a significant reduction in the dynamic power consumption of the row driver. For instance, employing the direct energy restoration technique resulted in a remarkable decrease of over 45% in the dynamic power consumption of the row driver.
Finally, a digital data driver with a data energy recycling feature is presented to further reduce the dynamic power consumption of microdisplays. Measurement results obtained from a proof-of-concept array fabricated using TSMC 65 nm technology demonstrate an average power consumption reduction of 16% in the display’s data driver when subjected to randomly generated test images.
This thesis addresses the pressing need for energy-efficient microdisplays, offering innovative driving methods, pixel circuit design, and dynamic power reduction techniques. The proposed solutions provide significant power savings while preserving display quality and enabling enhancements in resolution, refresh rate, and color depth, contributing to extended battery life and improved user experience in portable electronic systems
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