1,721,034 research outputs found
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
No full textMatlab codes relating to the article Al-Dujaily, Ra'ed, Li, An, Maunder, Robert G, Mak, Terrence, Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. IEEE Access.</span
Dataset supporting the paper entitled “A High-Speed Design Methodology for Inductive Coupling Links in 3D-ICs”
No full textThis dataset supports the article entitled 'A High-Speed Design Methodology for Inductive Coupling Links in 3D-ICs' accepted for publication in Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018</span
Design and optimization of inductive-coupling links for 3-D-ICs
No full textRecent research in the field of 3-D system integration has looked to the use of inductive-coupling links (ICLs) to provide vertical connectivity without incurring the inflated fabrication and testing costs associated with through-silicon vias. For power-efficient ICL design, optimization of the utilized physical inductor geometries is essential, but currently must be performed manually in a process that can take several hours. As a result, the generation of optimized inductor designs poses a significant challenge. In this paper, we address this challenge in three main contributions: 1) a novel, nonuniform planar inductor layout that exhibits enhanced performance when compared with conventional uniform inductors; 2) a rapid solver for evaluating inductor layouts; and 3) a high-speed optimization algorithm for determining best performing coil pairs. These three contributions are combined as a CAD tool for optimization of ICLs for 3-D-ICs (COIL-3-D). Results demonstrate that COIL-3-D achieves an average accuracy within 7.8% of finite-element tools consuming a small fraction of the time (1.5x 10E-3 %), significantly ameliorating the design of ICL-based 3-D-ICs. We also demonstrate that using COIL-3-D to optimize ICL inductor layouts can yield significant performance (up to 41.5% bandwidth improvement) and power (up to 8.1% power improvement) benefits, when compared with layouts used in prior ICL implementations. For these reasons, this paper unlocks new potential for low-cost, power-efficient 3-D integration using ICLs.</p
Dataset supporting the article entitled "Design and Optimisation of Inductive Coupling Links for 3D-ICs"
No full textThis dataset supports the article entitled "Design and Optimisation of Inductive Coupling Links for 3D-ICs" accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.</span
A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip
No full textIn 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.</p
A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration
No full textWireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35- μ m, 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7× improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.</p
Dataset supporting the article entitled "A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration"
No full textThis dataset supports the article entitled: 'A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration', accepted for publication in the ACM/IEEE International Symposium on Low Power Electronics and Design , Lausanne, 2019.</span
Eliminating synchronization latency using sequenced latching
No full textModern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative technique
Dataset supporting the article entitled "CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs"
No full textThis dataset supports the article entitled "CoDAPT: A Concurrent Data And Power
Transceiver for Fully Wireless 3D-ICs" accepted for publication in IEEE Design Automation and Test in Europe.</span
A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer
No full textThis paper presents a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus. The proposed design is the first implementation of a wireless link as part of a standard SoC bus, and achieves 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250um channel. This also makes it the smallest ever reported inductive data and power link
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