1,721,044 research outputs found
A Methodology to Estimate On-Voltage Degradation of Power Devices According to a Power Cycling Mission Profile
No full textAnalysis of thermal cycling effects in power devices under non-constant cumulative stress
No full textThis work experimentally investigates the reliability of TO-247 packaged power devices, with the goal of analyzing the impact of non-constant cumulative power cycling tests. Power devices are first stressed with a constant junction temperature cycling. Cumulative distribution function is experimentally evalu-ated and fitted with a Weibull statistics. According to the Miner's rule, the lifetime of components is calculated under a given non-constant cumulative stress at different levels of probabilities of failure. Experimental power cycling tests are then carried out to verify the accuracy of the predicted lifetime values
Influence of Power Cycling Test Methodology on the Applicability of the Linear Damage Accumulation Rule for the Lifetime Estimation in Power Devices
Full text linkThe lifetime of power semiconductor devices, operating under a given mission profile and subjected to power cycling stress, is conventionally estimated under the assumption of linear damage accumulation rule, that is the application of the Miner's rule. To this purpose, lifetime models must be properly defined allowing to take into account for the relevant parameters of power cycling stress. This work shows how to estimate a cumulative distribution function in the case of an arbitrary temperature swing profile, starting from the statistical distribution at constant power cycling conditions. It is found that the accuracy of the linear damage accumulation rule is related to the experimental methodology adopted for power cycling tests. A detailed experimental activity is carried out on packaged IGBT devices, providing useful guidelines for the definition of lifetime models to be adopted in the Miner's rule
Limiting power cycling stress in power MOSFETs by active thermal control
Full text linkIn this work we propose a system which is able to actively control the temperature of a power MOSFET, in order to limit the temperature swing and hence to reduce the power/thermal cycling effect. To this purpose a dedicated driving circuit, allowing to control the gate voltage of the switching device under investigation, is used in a synchronous buck converter. Therefore, power losses can be modulated in order to reach the desired temperature through self-heating effects. The implemented control system is able to compensate the non-linear relationship between the gate voltage and the on-resistance. Moreover, to improve the response of the system, a predictor has been implemented, having the capability of on-line tuning the thermal resistance of the device. Experimental results are reported to demonstrate the suitability of this solution to control the temperature in the semiconductor device. The reduction of temperature swing under power and thermal cycling is also demonstrated
Impact of Field-Plate Insulating Layer on Junction Breakdown Instability in OFT-Pw.MOSFET Devices
No full textIn this article, we investigate the junction breakdown instability in oxide-filled trench power MOSFETs, as a function of field-plate oxide characteristics. We compare the junction breakdown instability in devices adopting field-plate insulating layers thermally grown and low-pressure chemical vapor deposition process (LPCVD) deposited. We experimentally observe a different junction breakdown walk-out, depending on the field-plate insulating material. We found out that, by applying an electrical stress, besides the junction breakdown instability, a damage of the channel region is observed in the case of thermally grown field-plate oxide layer
Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress
Full text linkIn this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress
Remaining Useful Lifetime Prediction of Discrete Power Devices by Means of Artificial Neural Networks
Full text linkThis work proposes a deep learning-based model for predicting the lifetime of power devices subjected to power cycling. To this purpose, a neural network based on bidirectional long short-term memory is adopted. The neural network is trained with experimental on-voltage degradation profiles. The application of the proposed method is based on the monitoring of a precursor, that is the on-voltage degradation. According to considered precursor, the model allows predicting the remaining useful lifetime (RUL) of power components. In order to prove the accuracy of the model, TO-247 power devices are stressed under power cycling and their wear-out is experimentally investigated. RUL predicted by the neural network is then compared with the experimental lifetime of power devices. Thanks to the proposed deep learning model, the accuracy in the lifetime estimation improves as long as more information about the state of health of the device under test is acquired
Lifetime Prediction in Power Semiconductor Devices: A Comparative study between Analytical Modeling and Artificial Neural Network
No full textIn this work the reliability of TO-247 IGBT devices is investigated in the case of power cycling stress. A large range of test conditions is considered, varying the junction temperature cycling from 40°C to 150°C and the heating time from 0.3s to 32s. Under this wide range of test conditions, different failure modes determine the end of life of components. This work investigates the suitability of artificial neural networks and conventional analytical models to predict the lifetime of components where different failure mechanisms occur. Both models are compared against experimental data and root mean square relative errors are evaluated to quantify their accuracy
Simplified on-line monitoring system of MOSFET on-resistance based on a semi-empirical model
Full text linkThis work provides a solution allowing to monitor on-line the health of a power MOSFET adopted in a buck converter. In the considered application, the analysis is focused on the high-side switch, being a low-voltage power MOSFET. The monitoring system allows estimating the on-resistance of the device by measuring both output current and voltage drop across the switch. Moreover, a semi-empirical model is considered in order to account for the dependence of the on-resistance on operating temperature and gate driving voltage. The on-line implementation of such a model allows estimating on-resistance degradation in real-time with a high level of accuracy in a wide range of operating conditions. An on-line calibration procedure is also implemented in order to assess the on-resistance of fresh devices. Experimental results confirm the accuracy of the system (in conjunction with the proposed model) under different operating conditions: load current from 2A to 6A; device temperature up to 100°C and gate to source voltage (VGS) from 6V to 10.5V. In the abovementioned conditions, an accuracy ≤2.6% is experimentally found. Hence, the system is able to properly estimate the degradation of on-resistance due to ageing conditions
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