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Preface of the 2010 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems. Newswood Limited
Full text linkPreface of the 2011 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems
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Thermal modeling and analysis of a power ball grid array in system-in-package technology
Full text linkIn power electronics, system-in-package (SiP) designs require an approach for the development of an accurate thermal analysis which is different from traditional models. In fact, the power consumption alone of a SiP is not sufficient information for estimating the maximum temperature of the package or the temperature difference of the case when multiple power transistors are working in different configurations. In this paper, we propose a simple methodology to model the thermal behavior of a SiP circuit with eight power transistors and one integrated circuit (IC) driver in a fine pitch plastic ball grid array (BGA) package. The models are described for (i) the heat generation of the active components and (ii) the thermal analysis of the BGA package under test. The validation of the proposed thermal models was carried out through a comparison of the simulation results with experimental data, which were obtained from the thermal analysis by InfraRed thermography. The absolute estimation error was less than 2 ∘C for a maximum temperature of the BGA within 100 ∘C, and less than 4.5 ∘C for temperatures greater than 100 ∘C
Peak Power Constrained Test Sets: Generation Heuristics and Experiments
No full textLife-cycle and reliability of an electronic device are strictly related to the maximum (or peak) power the device dissipates in a single clock cycle. Particular care in situations of peak power violations should be taken in the testing phase of the design process. In such phase, the correctness of the circuit is checked by applying at its primary inputs a set of patterns properly selected with the purpose of detecting the presence of some faults. In a previous work we have addressed the problem of minimizing the peak power of a given combinational test set. The solution we have proposed generates test sets that guarantee a reduced peak power consumption at no penalty in fault coverage. In this paper, we present heuristic variants to the algorithm mentioned above. Such variants aim at increasing the efficiency of the test set, that is, they help better in controlling the size of the modified test set. We also investigate the impact of some of the parameters of the algorithm on the quality of the modified test set, and we support the conclusions we have drawn from the discussion with a large set of experimental data that we have collected on the Iscas'85 combinational benchmark circuit
Library Issues in the Implementation of Fast R2W Converters
No full textProperly choosing tire type and functionality of the cells being included in a technology library is essential to obtain efficient physical-level implementations of digital circuits; this is particularly true when the circuits are characterized by asymmetric logic structures and unbalanced input-to-output paths. In this paper, we report the results of an exploration we have conducted on the implementation of a high-throughput R2W conversion unit using a variety of libraries. Such results are exploited to assess advantages and drawbacks of the considered librarie
Power Simulation Using Test Sets: An Experimental Analysis
No full textIt happens often that designers utilize test sets for power simulation. This choice has three advantages: First, test vectors can be easily generated by efficient ATPG tools. Second, the number of patterns included in test sets is usually limited; this implies short simulation times. Third, since test vectors tend to sensitize most of the internal nodes of a circuit, a good distribution of the samples considered for power analysis is guaranteed. Unfortunately, using test vectors for power simulation has a drawback: In normal operation mode, only the most common functionalities of a circuit are exercised. On the contrary, test sets tend to sensitize a larger number of behaviors; therefore, there may be cases in which estimation results are not very accurate. In this paper, we provide results of an experimental investigation we have carried out on the use of test sets for power simulation. We report comparative data for standard benchmark circuits; in addition, we consider a realistic case study for which input streams can be generated using RTL simulatio
Exploring the Impact of Logic Synthesis on Area, Delay and Power Dissipation of CMOS Circuits
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