1,721,024 research outputs found
A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems
Full text linkThis paper presents a methodology for the system-level dependability analysis of multiprocessor embedded systems. The methodology is based on fault injection and features an error analysis approach offering to the designer the possibility to specify custom monitoring and classification actions at both application and architecture levels. In particular, a debug-like mechanism offers the possibility to interpret architectural raw data observed during the simulation at application level with a function call/return granularity, thus offering the possibility to analyze the propagation of the errors in the various functionalities of the executed application. A framework for automating the proposed methodology has been implemented within a state-of-the-art SystemC/TLM simulation platform for multiprocessor specifications provided with a fault injection engine. The effectiveness of the methodology has been demonstrated in two different case studies, showing how the proposed approach is able to produce an accurate dependability report highlighting the criticalities in both the architecture and the application of the system under design
Reliability-driven System-level Synthesis for Mixed-Critical Embedded Systems
No full textThis paper proposes a design methodology that enhances the classical system-level design flow for embedded systems to introduce reliability-awareness. The mapping and scheduling step is extended to support the application of hardening techniques to fulfill the required fault management properties that the final system must exhibit; moreover, the methodology allows the designer to specify that only some parts of the systems need to be hardened against faults. The reference architecture is a complex distributed one, constituted by resources with different characteristics in terms of performance and available fault detection/tolerance mechanisms. The approach is evaluated and compared against the most recent and relevant work, with an in-depth analysis on a large set of benchmarks
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs
No full textSelf-Adaptive Fault Tolerance in Multi-/Many-Core Systems
No full textThis paper presents a novel approach to the design of multi-/many-core systems with an adaptive level of reliability. The approach defines a layer at the operating system level that achieves fault detection/tolerance/diagnosis properties by means of thread replication and re-execution mechanisms. The layer applies the most convenient hardening mechanism to achieve the desired trade-off between reliability and performance by adapting at run-time to the changes of the working scenario. The proposed strategy has been applied in a set of experimental sessions considering a real-world parallel application, to evaluate its benefits on the final system with respect to various strategies selected at design time
Fault tolerance
No full textThe current trends in technology, fabrication processes, and computing architectures are increasingly pushing towards the design and development of multi-core and many-core systems constituted by a relevant number of relatively low-cost execution resources (e.g., processors and configurable accelerator units) to achieve high performance while leveraging on energy consumption. These trends must cope with increasingly unreliable devices, affected by the shrinking of component size, variations in the manufacturing process, and increased transient errors caused by radiations and noise fluctuations
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