1,721,176 research outputs found
Clock calibration faults and their impact on quality of high performance microprocessors
No full textIn this paper we analyze the fault effects of some clock calibration features which are common to today's high performance microprocessors. We show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g. scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that very deep sub-micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignore
Guest Editor's Introduction: Special Section on High Dependability Systems
No full textThe papers in this special section focus on high dependability systems. The continuous scaling of microelectronic technology has enabled electronic devices to become more and more pervasive and widespread. Nowadays most of the objects surrounding us include electronic devices, which are connected together through the Internet, creating the well-known Internet of Things. A huge amount of data is collected, processed and exchanged among these objects, on a daily basis. Humans’ life is becoming more and more dependent on decisions taken on the basis of such data and their processing. Autonomous vehicles and robots, trained and guided by such data, are becoming more and more popular. Their dependability (that is reliability, availability, safety and security) emerges as an obvious, mandatory constraint, that constitutes a challenge to enable the development of more and more autonomous systems. Major, worldwide efforts are consequently conducted to provide hardware and software solutions for high dependability systems
Low cost scheme for on-line clock skew compensation
No full textIn this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability
High speed and highly testable parallel two-rail code checker
No full textIn this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoint with respect to a wide set of realistic faults. The proposed checker is also particularly suitable to implement embedded two-rail code checkers, as it requires only two input codewords for fault detection. Our checker can be employed to check the correct operation of a connected functional block using the two-rail code, to implement the output two-rail code checker of "normal" checkers for un-ordered codes, or to join together the error messages produced by various checkers (possibly using different codes) present within the same self-checking system. The behavior of our checker has been verified by means of electrical level simulations (performed using HSPICE), considering both nominal values and statistical variations of electrical parameters
Error correcting codes for crosstalk effect minimization [system buses]
No full textIn this paper, we present an analysis of crosstalk effects on buses implementing error correcting codes. We show that the redundancy introduced by these codes can be exploited in order to avoid the worst case crosstalk-induced delay. Our analysis is based on the evaluation of the coupling effective capacitance which needs to be charged during bus activity. In particular, we analyze the cases of the Hamming and dual rail codes. We show that Hamming codes do not allow us to avoid the most delay costly bus transitions, while this can be the case for dual rail codes. Furthermore, we illustrate that, by increasing the redundancy of the dual rail code by only one bit, even higher crosstalk-induced delay reductions can be achieved. Finally, we show that a further improvement can be obtained by an optimized placing of the bus wires
Fast and compact error correcting scheme for reliable multilevel flash memories
No full textThis paper presents a method to reduce area and timing overhead due to the implementation of standard single symbol correcting codes to provide ML Flash memories with error correction ability. In particular, the proposed method is based on the manipulation of the parity check matrix which defines a code, which allows to minimize the matrix weight and the maximum row weight. Furthermore, we will show that a minimal increase in the redundancy, with respect to the standard case, allows a further considerable reduction of the impact on the memory access time, as well as on the area overhead due to the error correction circuitry
Crosstalk effect minimization for encoded busses
No full textIn this paper we present a technique which allows to reduce the crosstalk-induced delay within busses implementing an error detecting/correcting code. This technique is based on the observation that the maximum delay on an encoded bus is usually due to the check bits that are added to provide the desired error detection/ tolerance ability. These bits, in fact, are computed from the bus information bits by an ad hoc encoder, which adds an extra delay to the crosstalk-induced bus delay. We will show that, by proper placement of the lines carrying the information with respect to those carrying the check bits, it is possible to reduce the effective coupling capacitance due to the Miller effect among adjacent lines. This allows a reduction of propagation delay which, depending on the implemented code, can overcome the 20% with respect to the conventional placement of encoded busse
Novel high speed robust latch
No full textIn this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost
Transient fault and soft error on-die monitoring scheme
No full textIn this paper we propose an on-die monitoring scheme to detect and count transient faults (TFs) resulting, as well as not resulting in output SEs, affecting the inputs of data-path latches/flip-flops. This approach allows an early monitoring of the latches/flip-flops vulnerability to TFs, thus discovering intrinsic weaknesses of design or process. The proposed monitoring scheme features a very low impact on area overhead and power consumption, thus being suitable to be deployed within any IC
Secure communication protocol for wireless sensor networks
No full textWe propose a new communication protocol for wireless sensor networks, allowing to make them secure with respect to malicious attacks. Compared to standard secure protocols (e.g., the IEEE 802.15.4 and the ZigBee), the one we propose allows to increase security significantly, at negligible impact on node complexity. A possible hardware scheme to implement our protocol is also proposed
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