1,720,996 research outputs found
Statistical characterization, analysis and modeling of speed performance in digital standard cell designs subject to process variations
Full text linkA new logic level delay modeling paradigm for nano-CMOS standard cell variation-aware simulation
No full textLogic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs
No full textIn nanoscale digital CMOS IC design, the large technology parameter variations have boosted the interest in statistical performance analysis. As the huge execution time of SPICE-based transistor-level Monte Carlo analysis is impractical for complex designs, there is a need for making accurate Monte Carlo analysis feasible through fast logic-level simulators. This paper presents a new, general logic model of digital CMOS cells featuring technology variation aware timing, and its prototype implementation in a standard hardware-description-language environment. The application of the approach to typical standard cells and test circuits shows very good agreement with SPICE BSIM4 transistor-level simulation both for nominal delay and for statistical Monte Carlo analyses
A general design methodology for synchronous early-completion-prediction adders in Nano-CMOS DSP architectures
No full textSynchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works. © 2013 Mauro Olivieri and Antonio Mastrandrea
Optimal pipeline stage balancing in the presence of large isolated interconnect delay
No full textPipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneously distributed. When the target microarchitecture design includes isolated long interconnects, such as buses, optimal pipeline stage balancing becomes a tricky problem. This work formalises the solution based on the logical effort paradigm and evidences its advantage with respect to a heuristic approach
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs
No full textLogic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
No full textThe assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis
Full system emulation of approximate memory platforms with AppropinQuo
Full text linkIn this work we present an emulation framework for hardware platforms provided with approximate memory units, called AppropinQuo. The specific characteristic of AppropinQuo is to reveal the effects, on the hardware platform and on software, of errors introduced by approximate memory circuits and architectures. The emulator allows to execute software code without any modification with respect to the target physical board, since it includes the CPU, the memory hierarchy and the peripherals, capturing as well software-hardware interactions and faults due to approximate memory units. The final scope is reproducing the effects of errors generated by approximate memory circuits, allowing to evaluate the impact (quality degradation) on the output produced by the software. In fact, output quality is related to error rate, but their relationship strongly depends on the application, the implementation and its data representation on physical memory. The idea behind approximate memory circuits and approximate computing in general is to trade off energy consumption at the expense of computational accuracy and degradation of output quality. Memory is accounted for a large part of total power consumption in advanced architectures and it is supposed to increase as new memory hungry applications migrate toward the implementation on embedded systems (embedded machine learning, high definition video codecs, etc.). By relaxing design constraints regarding error probability on bit cells, researchers have proposed techniques that significantly reduce memory energy consumption. These techniques, which can be accounted in the general topic of approximate memory design, are implemented at circuit or architecture level, and are specific to the memory technology (i.e., SRAM or DRAM memories). However, the level of acceptable output degradation is the final metric that must be used to assess if, and to what extent, an approximate memory technique can be introduced. Our emulator allows to run actual applications as on the physical platform, to expose the effects of specific approximate memory circuits and architectures on output quality and to vary their parameters (e.g., error rate, number of affected bits, etc.). By exploring the approximate memory design space and its effects on the output of a software application, it is possible to characterize the application behavior, as a step toward the determination of the trade-off between saved energy and output quality (energy-quality tradeoff)
Contributions in evaluating the statistical impact of technology variations on delay and power dissipation of logic cells
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