1,355,046 research outputs found
Modeling of thermally induced skew variations in clock distribution network
No full textClock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning
No full textIn this paper, we propose a combined solution that allows us to customize the architecture of internally partitioned SRAM macros according to the given application be executed. Energy savings with respect to monolithic memory configurations are above 40%, without access time violation
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits
No full textPower-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We propose a new reactivation solution that helps in controlling power supply fluctuations and achieving minimum reactivation times. Our structure limits the turn-on current below a given threshold through a sequential activation of the sleep transistors (STs), which are connected in parallel and sized using a novel optimal sizing algorithm. We also introduce a distributed physical implementation, which allows minimum layout disruption after ST insertion and minimizes routing congestio
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating
No full textThe capability of accurately estimating an upper bound of the maximum current drawn by a digital macroblock from the ground or power supply line constitutes a major asset of automatic power-gating flows. In fact, the maximum current information is essential to properly size the sleep transistor in such a way that speed degradation and signal integrity violations are avoided. Loose upper bounds can be determined with a reasonable computational cost, but they lead to oversized sleep transistors. On the other hand, exact computation of the maximum drawn current is an NP-hard problem, even when conservative simplifying assumptions are made on gate-level current profiles. In this paper, we present a scalable algorithm for tightening upper bound computation, with a controlled and tunable computational cost. The algorithm exploits state-of-the-art commercial timing analysis engines, and it is tightly integrated into an industrial power-gating flow for leakage power reduction. The results we have obtained on large circuits demonstrate the scalability and effectiveness of our estimation approach
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
No full textLeakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts. We also introduce a clustering algorithm that is able to handle simultaneously timing and area constraints, and we extend it to the case of multi- Vt sleep transistors to increase leakage savings. The results we have obtained on a set of benchmark circuits show that the leakage savings we can achieve are, by far, superior to those obtained using existing power-gating solutions and with much tighter timing and area constraints
Low-Power Implementation of a Residue-to-Weighted Conversion Unit for a 5-Moduli RNS
No full textResidue Number Systems (RNSs) are integer systems that enable parallel execution of arithmetic operations. Therefore, they find a wide range of applications in DSP-oriented designs. Fundamental for making RNSs usable in portable systems is the availability of power-efficient residue-to-weighted (R2W) converters. In this paper we propose an implementation of a unit of this kind, based on the precomputation optimization paradigm, that shows a 27% reduction in average pourer dissipation with respect to an existing R2W architecture specifically designed to handle a 5-moduli RNS. The area and delay penalties are kept under control in the re-designed componen
Low-Overhead State-Retaining Elements for Low-Leakage MTCMOS Design
No full textMulti-threshold CMOS (MTCMOS) has shown to be a very effective technique for reducing sub-threshold leakage currents in DSM CMOS designs. Application of the MTC-MOS paradigm to sequential circuits requires the availability of data-retaining elements for storing circuit state during stand-by mode. In this paper we propose two novel circuit schemes for sequential elements featuring low leakage currents in stand-by mode and high-speed/low-dynamic power in active mode. We present post-layout simulation results obtained after parasitic extraction for delay and power of circuits built in 130nm CMOS technology. Our experiments demonstrate several advantages of the proposed schemes over the best previously published solutions
A Scalable Algorithmic Framework for Row-Based Power-Gating
No full textLeakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in standard cell based designs. In particular, we propose clustering algorithms for row-based power-gating methodology which is based on using rows of the layout as the granularity for clustering. Our clustering methodology does timing and area constraint driven power-gating in contrast to only timing driven power-gating as proposed in the previous works. We present two distinct clustering algorithms with different accuracy-efficiency trade-off. An optimal one, which exploits a 0-1 or Binary Integer Programming approach, and a heuristic one, which resorts to an implicit enumeration of the layout rows. Results show that, for all the benchmarks, the leakage power savings, as compared to previous techniques, are more than 75% when we have the same timing constraints but half sleep transistor area and at least 60% when area constraint is set at one fourth. We also show that we can perform clustering with no speed degradation and achieve maximum leakage power savings up-to 83
"Energy-Efficient Data Scrambling on Memory-Processor Interfaces"
No full textCrypto-processors are prone to security attacks based on the observation of their power consumption profile. We propose new techniques for increasing the non-determinism of such a profile, which rely on the idea of introducing randomness in the bus data transfers. This is achieved by combining data scrambling with energy-efficient bus encoding, thus providing high information protection at no energy cost. Results on a set of bus traces originated by real-life applications demonstrate the applicability of the proposed solutio
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