55 research outputs found
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors
No full textAbstract — Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communicationcentric interconnect fabrics, such as networks-on-chip (NoC), have been recently proposed. The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support. In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC. In particular, the paper focuses on the energy/delay exploration of on-chip physically distributed and logically shared memory address space for MP-SoCs based on a parameterizable NoC. The data allocation on the physically distributed shared memory space is dynamically managed by an on-chip Hardware Memory Management Unit. Experimental results show the impact of different NoC topologies and distributed shared memory configurations for a selected set of parallel benchmark applications from the power/performance perspective. I
The relevance of color in post COVID-19 interior design
No full textThe aim of this paper is to investigate the impact of thoughtful use of colors in post COVID-19 interior design and architecture, through the analysis of relevant case studies that challenge the definition of residential, work and hospitality spaces. Houses used to provide a private retreat from working and social activities, but in 2020 they abruptly took on new functions that once were prerogative of hotels and workspaces. This resulted in an extreme blurring of private and public spaces in the home, that can potentially have detrimental effects on the mental health and well-being of its occupants. Reconsidering essential elements of design practices, such as the chromatic definition and acoustics, could therefore help soothing the popular insecurities of the fruition of public places, well remark the role of private ones and further define new hybrid spaces, as shown by the research “Living, Working and Traveling”, curated by E. Elgani and F. Scullica
Self Reconfigurable Implementation of the JPEG Encoder
No full textDynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores dynamically alternate on the FPGA. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows for saving area with negligible performance overhead. We built a fully-working prototype, which demonstrates that the reconfigurable JPEG encoder achieves 29.6% area saving, 1.5% performance loss, and negligible power overhead with respect to a solution which uses statically mapped HW cores
Efficient Synchronization for Embedded on-Chip Multiprocessors
No full textThis paper investigates optimized synchronization
techniques for shared memory on-chip multiprocessors (CMPs)
based on network-on-chip (NoC) and targeted at future mobile
systems. The proposed solution is based on the idea of locally
performing synchronization operations requiring continuous
polling of a shared variable, thus, featuring large contentions (e.g., spin locks and barriers). A hardware (HW) module, the synchronization-operation buffer (SB), has been introduced to queue and to manage the requests issued by the processors. By using this mechanism, we propose a spin lock implementation requiring a constant number of network transactions and memory accesses per lock acquisition. The SB also supports an efficient implementation of barriers. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform for multiprocessor systems-on-chip (MPSoCs). Two different architectures have been explored to prove that the proposed approach is effective independently from caches and coherence schemes adopted. For an eight-processor target architecture, we show that the SB-based solution achieves up to 50% performance
improvement and 30% energy saving with respect to synchronization based on the caching of the synchronization variables and directory-based coherence protocol. Furthermore, we prove the scalability of the proposed approach when the number of processors increases
Direct writing of channel waveguide on a Tellurite glass using a focused ultraviolet Laser beam
No full textA dual-priority real-time multiprocessor system on FPGA for automotive applications
No full textThis paper presents the implementation of a dual-priority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkernel is supported by a multiprocessor interrupt controller to trigger periodic and aperiodic thread activation and manage context switching. We show how the dual-priority algorithm performs on a real system prototype compared to the theoretical performance simulations with a typical standard workload of automotive applications, underlining where the differences are
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach
No full textThe paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates
some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations,
matching the low-power characteristics of the target VLIW processors. Experimental results have been
carried out on Lx, an industrial 4-issue VLIW architecture
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA
No full textHigh performance multimedia applications are typical targets of today embedded systems. These applications, complex both in terms of execution flow and amount of elaborated data, can be well addressed by multiprocessor systems on-chip (MPSoCs). MPSoCs are composed of simple processors and memories tightly interconnected with fast communication channels and customized IP cores for the most demanding functions can be implemented and attached to these systems to enhance performance even more. Reconfigurable devices like FPGA, can act as a target, even programmed at runtime, for the custom IP cores, or as a prototyping platform for the whole system. Image compression like JPEG2000, can benefit very much from this approach and this type of architectures. This paper shows how the most demanding task of the JPEG2000 compression algorithm, the two-dimensional discrete wavelet transform, can be hardware accelerated and implemented in a multiprocessor system-on-chip prototyping platform on field programmable gate array (FPGA), CerberO. Architectures with different number of processors and hardware accelerators, shared among the processors or dedicated, have been implemented. To validate the approach, we show some experimental results on the platform with the hardware and the software implementation of the transformatio
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors
No full textMain goal of the paper is introducing a dynamic branch prediction scheme suitable for energy-aware VLIW (Very Long Instruction Word) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. Experimental results have been carried out on Lx/ST200, an industrial 4-issue VLIW architecture. We gathered two sets of results: First, by introducing the proposed low-power branch prediction technique in the Lx processor, which features fully static branch prediction, a significant improvement of the energy-delay metric has been observed. Second, we evaluated filtering efficacy of the proposed method and we found that it gets an access reduction to the branch prediction unit of 93% with respect to a processor directly derived from Lx, featuring cycle-by-cycle prediction, corresponding to an average 9% energy reduction of the whole processor power budget
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