66 research outputs found
Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
No full textAn increasing number of unhardened commercial-off-the-shelf embedded devices are deployed under harsh operating conditions and in highly-dependable systems. Due to the mechanisms of hardware degradation that affect these devices, ageing detection and monitoring are crucial to prevent critical failures. In this paper, we empirically study the propagation delay of 298 naturally-aged FPGA devices that are deployed in the European XFEL particle accelerator. Based on in-field measurements, we find that operational devices show significantly slower switching frequencies than unused chips, and that increased gamma and neutron radiation doses correlate with increased hardware degradation. Furthermore, we demonstrate the feasibility of developing machine learning models that estimate the switching frequencies of the devices based on historical and environmental data.If you cite this paper, please use the DSD reference: Leandro Lanzieri, Lukasz Butkowski, Jiri Kral, Goerschwin Fey, Holger Schlarb, and Thomas C. Schmidt. Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. In Proceedings of the 27th Euromicro Conference on Digital System Design (DSD), IEEE, 202
A Model Based Fast Protection System for High Power RF Tube Amplifiers Used at the European XFEL Accelerator
No full textThe driving engine of the superconducting accelerator of the European X-ray free electron laser (XFEL) is a set of 27 radio frequency (RF) stations. Each of the underground RF stations consists of a multibeam horizontal klystron that can provide up to 10 MW of power at 1.3 GHz. Klystrons are sensitive devices with a limited lifetime and a high mean time between failures. In real operation, the lifetime of the tube can be significantly reduced because of failures. The special fast protection klystron lifetime management (KLM) system has been developed to minimize the influence of service conditions on the lifetime of klystrons. The main task of this system is to detect all events which can destroy the tube as quickly as possible, and switch off the driving RF signal or the high voltage. Detection of events is based on a comparison of the value of the real signal obtained at the system output with the value estimated on the basis of a high-power RF amplifier model and input signals. The KLM system has been realized in field-programmable gate array (FPGA) and implemented in XFEL. Implementation is based on the standard low-level RF micro telecommunications computing architecture (MTCA.4 or xTCA). The main part of the paper focuses on an estimation of the klystron model and the implementation of KLM in FPGA. The results of the performance of the KLM system will also be presented
The Self Excited Loop Cavity Field Controller and the Cavity Simulator Implemented in MTCA.4 System
No full textThe superconducting cavity vertical test stand at DESY is going to be updated with the MTCA.4 based system. The digital self exited loop (SEL) LLRF controller has been developed to fulfill the requirements for the controller to drive the cavity with high QL up to 1e10 and high cavity detuning up to 10kHz. In order to test the SEL controller, additionally the real-time cavity simulator has been developed. The electrical and mechanical model of a cavity represented by a differential equation, is implemented inside the FPGA. The model takes the forward power as an input and produces a probe signal based on given detuning and half-bandwidth parameters of a cavity. Microphonic disturbance is also added to simulate the high Ql operation.Both, the cavity simulator and the SEL controller has been implemented in the SIS8300KU, DRTM-DW8VM1 pair boards
Klystron Measurement and Protection System for XFEL on the uTCA Architecture
No full textThe European XFEL free-electron laser is under construction at the DESY. The driving engineof the superconducting accelerator will be 27 RF station. Each of an underground RF stationconsist from multi beam horizontal klystron which can provide up to 10MW of power at1.3GHz. The XFEL should work continuously over 20 years with only 1 day per month formaintenance. In order to meet so demanding requirement lifetime of the MBK should be aslong as possible. In the real operation the lifetime of tube can be thoroughly reduced by serviceconditions. To minimize the influence of service conditions to the klystrons lifetime thespecial fast protection system named as Klystron Lifetime Management System (KLM) hasbeen developed, the main task of this system is to detect all events which can destroy thetube as quickly as possible, and then stop input power to the tube and send signal to stopHV pulse. The tube recovery procedure should depend on the kind of events has happened.KLM is based on the standard LLRF uTCA system for XFEL with additional DC channels.This article gives an overview of implementation of measurement and protection systeminstalled at klystron test stand
Rapid FPGA Development Framework Using a Custom Simulink Library for MTCA.4 Modules
No full textThe recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. It required the development to move away from traditional programming languages (C/C++) to hardware description languages Verilog), which are used in FPGA development.. With MATLAB/Simulink it is possible to describe complex systems with block diagrams and simulate their behavior. Those diagrams are then used by the HDL experts, to implement exactly the required functionality in hardware. Both the porting of existing applications and adaptation of new ones requires a lot of development time from them. To solve this, Xilinx SystemGenerator, a toolbox for MATLAB/Simulink, allows rapid prototyping of those block diagrams using hardware modelling. It is still up to the firmware developer to merge this structure with the hardware-dependent HDL project. This prevents the application engineer from quickly verifying the proposed schemes in real hardware.The framework described in this article overcomes these challenges, offering a hardware-independent library of components that can be used in Simulink/SystemGenerator models. The components are subsequently translated into VHDL entities and integrated with a pre-prepared VHDL project template. Furthermore, the entire implementation process is run in the background, giving the user a one-click path from control scheme modelling and simulation to bit-file generation.This approach allows the control theory engineers to quickly develop new schemes and test them in real hardware environment. The applications may range from simple data logging or signal generation ones to very advanced controllers. Taking advantage of the Simulink simulation capabilities and user-friendly hardware implementation routines, the framework significantly decreases the development time of FPGA-based applications
Controller Latency Improvements at REGAE
No full textREGAE is a facility for ultrafast electron diffraction (UED) experiments based on a normal conducting S-band gun and buncher cavity. Their RF regulation is performed by a single cavity controller, implemented by an FPGA firmware and operating at 125 MHz. With a variant of the Struck SIS8300-KU controller board that is equipped with 250 MSps ADCs we were able to increase the frequency of the complete digital processing chain to 250 MHz. This includes the ADCs, field detection, feedback controller and DAC. Doubling the frequency reduced the overall controller latency by almost a factor of two. In the poster we show which firmware components had to be optimized or rewritten to achieve the 250 MHz clock rate
Optimization of Klystron Drive Signal and HV Shape to Reduce Energy Consumption during Operation of the European XFEL
No full textCurrently 26 RF stations are in operation at the European X-ray Free Electron Laser (XFEL) and all RF stations can deliver sufficient power to support 600 µs beam pulse with an energy up to 17 GeV. These beam parameters require a power consumption of about 4.9 MW for high-power RF. Of course, the simplest way to save power is to reduce the XFEL repetition rate, but with some additional work and research, and without modifying any hardware, we can save the modulator power, without any impact on the XFEL performance. To reduce the power, we offer two methods that can be used together or separately. The first one is to make full use of the available power of the klystron during the rise and fall time of the HV pulse, and partial use of the available power during cavity filling by using phase and amplitude compensation. As a result, we can reduce the length of the HV pulse, because we fill the cavities with energy earlier. The second one is to slowly reduce the klystron HV during flattop. In total we can reduce the power consumption up to 30%, at the cost of making the LLRF control more complicated as it needs to deal with large phase and amplitude changes. To solve this problem, we propose two possibilities: first, feed-forward table rotation, and second, the addition of a feedback loop for the klystron. In this report we will present some of experimental results from the klystron test stand and from several XFEL RF stations
Real-Time Cross-Coupling removal and Monitoring in RF feedback systems: HLS-based FPGA implementation
No full textImplementing digital signal processing (DSP) solutions on FPGAs is a challenging task that requires technical knowledge of the system and the functionality of algorithms. Using High-Level Synthesis (HLS) tools for handling DSP tasks accelerates the implementation process and reduces the development stage. Moreover, HLS solutions decrease FPGA verification time and provide flexibility for configuring design parameters with extensive iteration capabilities. In this paper, hardware accelerator units are introduced to correct the driven Radio Frequency (RF) signals in Low-Level RF (LLRF) multi-cavity controller systems. In RF stations, a portion of the injected signal into cavities is reflected due to the load mismatch and also the mismatch in the frequency of the forward signal and the resonance frequency of cavities. The presented design improves the quality of the measurements in multi-cavity stations by real-time removal of the cross-coupling effect from the signal. This is achieved using the concepts of pipelining, parallelism, and the proper usage of FPGA resources for DSP calculation. Moreover, the paper introduces a real-time monitoring system for RF systems. Proposed units are used for detecting anomalies in the system by comparing the actual probe signal from each station with the virtual probe calculated based on the input signal. The main benefits of this solution are real-time calculation of corrected signals using DSP techniques and the introduction of an anomaly detector. Furthermore, this design reduces the workload from other parts of the system with off-load correction and monitoring of the RF cavities, leading to the better performance of the overall system
An MTCA.4 Based Position Feedback Application Using Laserinterferometers
No full textTo perform experiments on the nanometer scale at high brilliant x-ray light sources, it is highly recommended to have the mechanical components of the experiment, like lenses, mirrors and samples, as stable as possible. Since these components need to move from nanometer up to millimeter range they cannot be stabilized by only using rigid structures. For that reason an active stabilization system with fast and precise sensors needs to be developed. Here a Laserinterferometer is used, which provides picometer resolution at several MHz sample rate. In this paper we will present a laboratory setup which consists of a 6-slot Micro Telecommunication Computing Architecture generation 4 (MTCA.4) crate with standard components such MicroTCA carrier hub (MCH), central processing unit (CPU), power supply (PS) and cooling unit (CU). The Interferometer application has been setup with Deutsches Elektronen-Synchrotron (DESY) advanced mezzanine card (DAMC-FMC20) data processing unit, DESY Field Programmable Gate Array (FPGA) mezzanine card (DFMC-UNIO) universal input and output extension and DESY rear transition module (DRTM-PZT4) piezo driver. The encoder signals given by the interferometer controller are processed within the FPGA and then forwarded to the piezo amplifier RTM-board. The signal processing application includes decoding the digital feedback signal, calculating the coordinate transform for specific experimental setups and closed-loop operation based on a proportional integral derivative (PID) controller. The first results of the laboratory setup are demonstrated and briefly discussed
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