44 research outputs found
Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications
No full textThe fractional-N frequency synthesis based on Digital Phase Locked Loop
(DPLLs) has become a conventional design approach for the new radio wireless
applications. The advantage of the digitally-intensive design style is the possibility
to implement low-power and very accurate digital calibration techniques. Most of
these algorithms run in the background tracking PVT variations and either relax
or, in some cases, completely remove the performance limitations due to analog
impairments. Moreover, the digital loop filter area is practically negligible with
respect to the one in analog PLLs. These benefits become even more relevant in
the scaled CMOS technology nodes. This chapter identifies the design parameters
of a standard DPLL architecture and proposes a novel locking scheme to overcome
the intrinsic limitations of the digital frequency synthesizers approach. To prove this
new scheme a sub-6GHz fractional-N synthesizer has been implemented in 65nm
CMOS. The synthesizer has an output frequency from 3.59GHz to 4.05GHz. The
integrated output jitter is 182fs and the power consumption of 5.28mW from 1.2V
power supply leads to a FoM of -247.5dB. This topology exploits a novel locking
technique that guarantee a locking time of 5.6s, for a frequency step of 364MHz,
despite the use of a single bit phase detector
Analysis of power efficiency in high-performance class-B oscillators
No full textThis paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class-B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves a phase noise of -159 dBc/Hz at 20-MHz offset from the 3.6-GHz carrier, while dissipating 4.5 mW from 1.2-V power supply and covering 21.8% tuning range
LATCH COMPARATOR
No full textThe invention consists in a single-stage FIA-based comparator with an embedded latch, which is insensitive to input common-mode voltage variations.
With respect to the state-of-the-art FIA-based comparator architectures, the invention:
a) has a simpler implementation, because of the single-stage topology, eliminating the interface between the pre-amp and the latch;
b) does not require the design of additional logic gates to open the reservoir switches since the circuit already incorporates a self-quenching mechanism that automatically stops the reservoir capacitor discharge
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
No full textDigital PLLs (DPLLs) have demonstrated to be a promising candidate to implement frequency synthesizers in wireless transceivers, thanks to their scaling-friendly architecture and to the possibility of implementing powerful background adaptive calibration algorithms to compensate the system non-idealities. The combination of these features leads to an inherently faster time-to-market than traditional analog PLLs, avoiding lengthy porting and redesign phases and factory calibrations, making DPLLs particularly attractive to cope with the surge of mobile applications recently driven by remote working and contactless businesses. Among DPLLs, bang-bang DPLLs are especially attractive for their reduced complexity and low power consumption, thanks to the use of a binary phase detector (BPD), while still capable of achieving state-of-the-art phase noise, jitter, and fast-lock performances [1]–[2]. However, the DPLL bandwidth, on top of being subject to process, voltage, and temperature (PVT) variations, also depends on the system phase noise level [3]
NESTED FLOATING-INVERTER BASED AMPLIFIER
No full textIn accordance with an embodiment, a nested floating inverter dynamic amplifier (FIDA) includes: a first FIDA amplifier comprising a plurality of first inverters switchably coupled to a first reservoir capacitor; and a second FIDA amplifier comprising a plurality of second inverters switchably coupled to a second reservoir capacitor, wherein outputs of the plurality of first inverters are coupled to corresponding inputs of the plurality of second inverters
Digital PLLs: the modern timing reference for radar and communication systems
No full textDigital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS. This paper will briefly trace the path from the (re-)discover of this approach to the more recent solutions, discussing the main characteristics of key building blocks and their limitations, both the ones that can be removed by digital calibrations, such as the non-linearities, and the most fundamental one, the noise, that still calls for a sound knowledge of analog design techniques. Recent results are also presented and perspectives discussed
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity
No full textIn this paper, we present a novel input buffer based on the push-pull architecture for an 11-bit 2-GS/s 8x time-interleaved ADC. The proposed buffer features an auxiliary follower which is used to drive the body terminals of the main push-pull output transistors, removing their non-linear contribution at the output node, with a negligible overhead in terms of power consumption. The ADC features a 0.9-V reference voltage and requires an input common-mode voltage of 0. 45V. The proposed buffer, designed in a 28-nm CMOS technology, achieves better than 73-dB Spurious-Free Dynamic Range (SFDR) in the 1-GHz Nyquist bandwidth, which is up to 6.3dB better than the conventional push-pull topology, burning 38mW from +1.8/-1V supplies, including the bias circuit
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
No full textDigital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process
No full textThis work presents a Time-to-Digital Converter
(TDC) for Digital Phase-Locked Loops (DPLLs) applications featuring
a dynamic power-reduction technique. The architecture,
implemented in a 28-nm CMOS technology with a 0.9-V supply
voltage and 250MHz sample rate, is able to reduce its power
consumption up to 47% compared to the same TDC without
the proposed solution, dissipating a minimum of 33μW during
normal operation
A Multi-Input Error-Feedback Architecture for Noise-Shaping SAR ADCs
No full textThe invention consists of a new architecture for error-feedback (EF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) (Fig. 1). The fundamental components of the new implementation are a multi-input comparator (MIC) and a multi-input amplifier (MIA). In the new architecture, the position of the poles and zeros of the noise transfer function (NTF) is well controlled by component ratios within the MIC and the MIA.
Figure 1. Circuit implementation of the 1st-order multi-input (MI) EF invention.
Compared to currently available solutions, the present invention significantly reduces the noise of the switched-capacitor circuit following the amplifier, resulting in reduced area and power consumption of the amplifier
