1,720,999 research outputs found
Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation
Full text linkWe present a study based on numerical simulations and comparative analysis of recent experimental data concerning the operation and design of FeFETs. Our results show that a proper consideration of charge trapping in the ferroelectric-dielectric stack is indispensable to reconcile simulations with experiments, and to attain the desired hysteretic behavior of the current-voltage characteristics. Then we analyze a few design options for polysilicon channel FeFETs and, in particular, we study the influence of the channel thickness and doping concentration on the memory window, and on the ratio between the polarization dependent, high and low resistance state
Multi-level Operation of FeFETs Memristors: The Crucial Role of Three Dimensional Effects
No full textThis paper investigates and compares through a comprehensive TCAD analysis 2D and 3D simulations for ferro-electric based FETs. We provide clear evidence that the multiple read conductance values experimentally observed in FeFETs stem from source to drain percolation current paths, which are governed by the polarization patterns in the ferroelectric domains. Such a physical picture makes 3D simulations indispensable to capture even the qualitative features of the device behaviour, not to mention the quantitative aspects
Multilevel Operation in Scaled Back-End-of-Line Ferroelectric FETs With a Metal Interlayer
Full text linkMulti-level operation, conventionally obtained in ferroelectric devices thanks to a domain-dependent inhomogeneous polarization, poses a big challenge for highly-scaled ferroelectric devices, where the number of ferroelectric domains is drastically reduced. In this work, we study a highly scaled back-end-of-line (BEOL) compatible, ferroelectric field-effect transistor (FeFET) that integrates a metal interlayer in the gate stack. Through analytical models and calibrated TCAD simulations, we show how this device can achieve a multi-level operation exploiting the interplay between the ferroelectric polarization and the charge in the metal interlayer. Such a working principle does not rely on a domain-dependent inhomogeneous polarization, and the device operation is thus ensured also for a homogeneous ferroelectric material. We also demonstrate that the charge in the interlayer can effectively stabilize the ferroelectric polarization even in the absence of a high concentration of trapped charges in the gate stack. The potentiation and depression curves for the readout conductance confirm that the proposed device can be operated as a memristor for neuromorphic computing applications. Moreover, we show how the choice of the dielectric in the metal-ferroelectric-dielectric-metal gate stack can be used as a design knob to reduce the device operation voltage
Limitations to Electrical Probing of Spontaneous Polarization in Ferroelectric-Dielectric Heterostructures
Full text linkAn accurate estimate of the ferroelectric polarization in ferroelectric-dielectric stacks is important from a materials science perspective, and it is also crucial for the development of ferroelectric based electron devices. This paper revisits the theory and application of the PUND technique in Metal-Ferroelectric-Dielectric-Metal (MFDM) structures by using analytical derivations and numerical simulations. In an MFDM structure the results of the PUND technique may largely differ from the polarization actually switched in the stack, which in turn is different from the remnant polarization of the underlying ferroelectric. The main hindrances that prevent PUND measurements from providing a good estimate of the polarization switching in MFDM stacks are thus discussed. The inspection of the involved physical quantities, not always accessible in experiments, provides a useful insight about the main sources of the errors in the PUND technique, and clarifies the delicate interplay between the depolarization field and the charge injection and trapping in MFDM stacks with a thin dielectric layer
Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme
Full text linkWe present a new model for surface roughness (SR) scattering in n-type multi-gate FETs (MuGFETs) and gate-all-around nanowire FETs with fairly arbitrary cross-sections, its implementation in a complete device simulator, and the validation against experimental electron mobility data. The model describes the SR scattering matrix elements as non-linear transformations of interface fluctuations, which strongly influences the root mean square value of the roughness required to reproduce experimental mobility data. Mobility simulations are performed via the deterministic solution of the Boltzmann transport equation for a 1D-electron gas and including the most relevant scattering mechanisms for electronic transport, such as acoustic, polar, and non-polar optical phonon scattering, Coulomb scattering, and SR scattering. Simulation results show the importance of accounting for arbitrary cross-sections and biasing conditions when compared to experimental data. We also discuss how mobility is affected by the shape of the cross-section as well as by its area in gate-all-around and tri-gate MuGFETs. © 2017 Author(s)
Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating
Full text linkTremendous improvements in the fabrication
technology have allowed to scale the physical dimensions
of the transistors and also to develop different promising
3-D architectures that may allow continuing Moore’s law.
In this paper, we perform a comparative delay analysis of different
3-D device architectures and study the impact of surface
roughness and self-heating on the on-current using a
comprehensive in-house simulation framework comprising
Schrödinger, Poisson, and Boltzmann transport equation
solvers and comprising relevant scattering mechanisms
and self-heating. Our results highlight that parasitic capacitance
can alter the relative ranking of the architectures from
delay point of view. We demonstrate that surface roughness
can cause architectureand material-dependentcurrent
degradation, and hence, it is necessary to account for it in
simulation-based benchmarking different architectures
Ohmic Behavior in Metal Contacts to n/p-Type Transition-Metal Dichalcogenides: Schottky versus Tunneling Barrier Trade-off
Full text linkHigh contact resistance (RC) between 3D metallic conductors and single-layer 2D semiconductors poses major challenges toward their integration in nanoscale electronic devices. While in experiments the large RC values can be partly due to defects, ab initio simulations suggest that, even in defect-free structures, the interaction between metal and semiconductor orbitals can induce gap states that pin the Fermi level in the semiconductor band gap, increase the Schottky barrier height (SBH), and thus degrade the contact resistance. In this paper, we investigate, by using an in-house-developed ab initio transport methodology that combines density functional theory and nonequilibrium Green’s function (NEGF) transport calculations, the physical properties and electrical resistance of several options for n-type top metal contacts to monolayer MoS2, even in the presence of buffer layers, and for p-type contacts to monolayer WSe2. The delicate interplay between the SBH and tunneling barrier thickness is quantitatively analyzed, confirming the excellent properties of the Bi-MoS2 system as an n-type ohmic contact. Moreover, simulation results supported by literature experiments suggest that the Au-WSe2 system is a promising candidate for p-type ohmic contacts. Finally, our analysis also reveals that a small modulation of a few angstroms of the distance between the (semi)metal and the transition-metal dichalcogenide (TMD) leads to large variations of RC. This could help to explain the scattering of RC values experimentally reported in the literature because different metal deposition techniques can result in small changes of the metal-to-TMD distance besides affecting the density of possible defects
Editorial: Letters from the 8th Joint International EUROSOI workshop and International Conference on Ultimate Integration on Silicon
No full textModelling and Simulations of Ferroelectric Materials and Ferroelectric-Based Nanoelectronic Devices : (Invited Paper)
No full textThis paper provides a brief introduction to the phenomenological aspects of the polarization in ferrroelectric materials, and then an analysis of a few selected topics related to the modelling of ferroelectrics. The description of ferroelectric-based devices is quite challenging, particularly because the ferroelectric is frequently stacked with other dielectrics or with a semiconductor, as opposed to being placed between metal electrodes. Predictive modelling of ferroelectric devices is admittedly difficult, and thus the scrutiny and calibration of the models by comparison to sound experimental data is of paramount importance
Editorial: Selected papers from the 8th Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2022)
No full text- …
