1,720,993 research outputs found
Advanced models for simulation of planar and gate-all-around nanoscale MOSFETs
Full text linkThe aim of this thesis is the development and validation of TCAD tools for both the purpose of device performance analysis and performance improvement.
We first present a comparative simulation study of ultra-thin-body strained silicon and III-V semiconductor based MOSFETs by using a comprehensive semiclassical Multisubband Monte Carlo transport model.
We then present a new model for the surface roughness scattering. The model is suitable for bulk, for ultra-thin-body and for hetero-structure quantum well MOSFETs. Comparison with experimental mobility for Si bulk MOSFETs shows that a good agreement with measured mobility can be obtained with a r.m.s. value of the surface roughness spectrum close to several AFM and TEM measurements.
Finally, we developed a deterministic solver for the Boltzmann transport equation for gate-all-around circular MOSFETs. In particular, we solve the Schrodinger equation for arbitrary crystal transport directions within the effective mass approximation including the wave-function penetration into the oxide and the nonparabolicity of the energy dispersion relation along the quantization plane and transport direction.
Then, the BTE is solved without any a-priori assumption and including the main scattering mechanisms responsible for performance degradation, with a new model for the SR scatterin
Modelling and Design of Short Channel Ferroelectric FETs with a Metal Interlayer Easing the Multilevel Operation
No full textThis work presents a simulation study of a ferroelectric field effect transistor (FeFET), which leverages a metal interlayer to achieve a multilevel operation thanks to the interplay between the ferroelectric polarization and the charge stored in the interlayer. We show that the metal interlayer can effectively stabilize the ferroelectric polarization even for a negligible charge trapping in the dielectric stack and, moreover, enable a multilevel operation even for a uniform ferroelectric polarization
Performance of III-V nanoscale MOSFETs: a simulation study
No full textChannel materials alternative to silicon have been recently introduced as a new scaling scenario to operate at increasingly lower supply voltages and maintain high performance. Silicon-based devices might reach their scaling limit imposed by the fundamental physical properties of silicon in the next few years making it difficult to achieve the expected performance
for the future CMOS [6]. While for pMOS transistors promising results have been obtained by using the Ge as channel material [7], the best candidates for nMOS transistors are III-V semiconductors
Performance Benchmarking and Effective Channel Length for Nanoscale InAs, In0.53Ga0.47As, and sSi n-MOSFETs
No full textThanks to the high electron velocities, III–V
semiconductors have the potential to meet the challenging ITRS
requirements for high performance for sub-22-nm technology
nodes and at a supply voltage approaching 0.5 V. This paper
presents a comparative simulation study of ultrathin-body InAs,
In0.53Ga0.47As, and strained Si MOSFETs, by using a comprehensive
semiclassical multisubband Monte Carlo (MSMC)
transport model. Our results show that: 1) due to the finite
screening length in the source-drain regions, III–V and Si
nanoscale MOSFETs with a given gate length (LG) may have
a quite different effective channel length (Leff); 2) the difference
in Leff provides a useful insight to interpret the performance
comparison of III–V and Si MOSFETs; and 3) the engineering
of the source-drain regions has a remarkable influence on the
overall performance of nanoscale III–V MOSFETs
Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel
No full textThis paper reports a simulation study investigating
the drive current of a prototypical SiGe n-type FinFET built
on a relaxed SiGe substrate for different values of the Ge
content x in the Si(1−x)Gex active layer. To this purpose, we
performed strain simulations, band-structure calculations, and
multisubband Monte Carlo transport simulations accounting for
the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering
Reinterpreting Low Resistance in Sb–MoS2 Ohmic Contacts by Means of Ab Initio Transport Simulations
Full text linkBy using an in-house nonequilibrium Green’s function (NEGF)-based ab initio simulator, we investigate the physical mechanisms driving the Sb(0112)–MoS2 system to exhibit the lowest reported contact resistance, RC =42 Ω·μm, to the 2-D semiconductor MoS2. We can find that the transport from the hybridized bands in the Sb–MoS2 heterojunction is quite ineffective and that the back-gateinduced doping of MoS2 in the contact region is crucial to explain the experiments. In fact, by accounting in our ab initio simulations for the presence of a back gate according to the experiments, it is possible to match the band structure of the MoS2 in the Sb–MoS2 heterojunction with that of the external MoS2 layer, which drastically increases the electronic transmission throughout the contact, and ultimately pushes RC close to the quantum limit. Furthermore, we extend the applicability of our previously demonstrated simulation methodology and thus investigate a field-effect transistors (FETs)-like device including an ab initio description of the carrier injection at the Sb–MoS2 contac
An LGD model with extrinsic nucleations for polarization dynamics in ferroelectric materials and devices
Full text linkAbstract We present a critical reexamination of the Landau–Ginzburg–Devonshire (LGD) model for ferroelectric materials that is based on intrinsic nucleation events. Theoretical considerations and a systematic comparison with experiments steered us towards a novel version and calibration of the LGD model relying instead on extrinsic nucleations. We show that the new model can not only improve the agreement with experiments, but also help reconcile the interpretation of polarization reversal in poly-crystalline and epitaxial ferroelectrics
A new formulation for surface roughness limited mobility in bulk and ultra-thin-body metal–oxide–semiconductor transistors
No full textThis paper presents a new model for the surface roughness (SR) limited mobility in MOS transistors. The model is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement of the interface position and the SR scattering matrix elements, which is found to significantly influence the r.m.s value of the interface roughness that is necessary to reproduce SR-limited mobility measurements. In particular, comparison with experimental mobility for bulk Si MOSFETs shows that with the new SR scattering model a good agreement with measured mobility can be obtained with r.m.s. values of about 0.2 nm, which is in good agreement with several AFM and TEM measurements. For thin body III–V MOSFETs, the proposed model predicts a weaker mobility degradation at small well thicknesses (Tw), compared to the Tw^6 behavior observed in Si extremely thin body device
Surface roughness limited mobility modeling in ultra-thin SOI and quantum well III-V MOSFETs
No full textThis paper presents a new model for the surface roughness
(SR) limited mobility (μSR). The model is suitable for bulk,
for ultra thin body (UTB) and for Hetero-Structure Quantum
Well (HS-QW) MOSFETs. Comparison with experimental
mobility for Si bulk MOSFETs shows that a good agreement
with measured mobility can be obtained with a r.m.s. value
of the SR spectrum close to several AFM and TEM measurements.
For III-V MOSFETs with small well thickness the
proposed model shows a weaker mobility degradation with
respect to the Tw6 behavior
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