1,721,108 research outputs found
BOOM: Broadcast Optimizations for On-chip Meshes
Get PDFFuture many-core chips will require an on-chip network that can support broadcasts and multicasts at good power-performance. A vanilla on-chip network would send multiple unicast packets for each broadcast packet, resulting in latency, throughput and power overheads. Recent research in on-chip multicast support has proposed forking of broadcast/multicast packets within the network at the router buffers, but these techniques are far from ideal, since they increase buffer occupancy which lowers throughput, and packets incur delay and power penalties at each router. In this work, we analyze an ideal broadcast mesh; show the substantial gaps between state-of-the-art multicast NoCs and the ideal; then propose BOOM, which comprises a WHIRL routing protocol that ideally load balances broadcast traffic, a mXbar multicast crossbar circuit that enables multicast traversal at similar energy-delay as unicasts, and speculative bypassing of buffering for multicast flits. Together, they enable broadcast packets to approach the delay, energy, and throughput of the ideal fabric. Our simulations show BOOM realizing an average network latency that is 5% off ideal, attaining 96% of ideal throughput, with energy consumption that is 9% above ideal. Evaluations using synthetic traffic show BOOM achieving a latency reduction of 61%, throughput improvement of 63%, and buffer power reduction of 80% as compared to a baseline broadcast. Simulations with PARSEC benchmarks show BOOM reducing average request and network latency by 40% and 15% respectively
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
No full textEditor\u27s note: The diversification of the SoC market has increased the need for domain-specific programmable platforms that can be tailored to ostfabrication products. This article presents a design case study on the interconnect for such a programmable platform, as part of the Morpheus project Li-Shiuan Peh, Princeton Universit
DESIGN OF WEARABLE APPLICATIONS AND PLATFORMS FOR NEXT GENERATION PERSONALIZED SENSING
No full textPh.DDOCTOR OF PHILOSOPHY (CDE-ENG
Design and implementation of low-latency, low-power reconfigurable on-chip networks
No full textThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.Cataloged from PDF version of thesis.Includes bibliographical references (pages [159]-187).In this dissertation, I tackle large, low-latency, low-power on-chip networks. I focus on two key challenges in the realization of such NoCs in practice: (1) the development of NoC design toolchains that can ease and automate the design of large-scale NoCs, paving the way for advanced ultra-low-power NoC techniques to be embedded within many-core chips, and (2) the design and implementation of chip prototypes that demonstrate ultralow- latency, low-power NoCs, enabling rigorous understanding of the design tradeoff of such NoCs. I start off by presenting DSENT (joint work), a timing, area and power evaluation toolchain that supports flexibility in modeling while ensuring accuracy, through a technology-portable library of standard cells [108]. DSENT enables rigorous design space exploration for advanced technologies, and have been shown to provide fast and accurate evaluation of emerging opto-electronics. Next, low-swing signaling has been shown to substantially reduce NoC power, but requires custom circuit design in the past. I propose a toolchain that automates the embedding of low-swing cells into the NoC datapath, paving the way for low-swing signaling to be part of future many-core chips [17]. Third, clockless repeated links have been shown to be embeddable within a NoC datapath, allowing packets to go from source to destination cores without being latched at intermediate routers. I propose SMARTapp, a design that leverages theses clockless repeaters for configuration of a NoC into customized topologies tailored for each applications, and present a synthesis toolchain that takes each SoC application as input, and synthesize a NoC configured for that application, generating RTL to layout [18]. The thesis next presents two chip prototypes that I designed to obtain on-depth understanding of the practical implementation costs and tradeoffs of high-level architectural ideas. The SMART NoC chip is a 3 x 3 mm2 chip in 32 nm SOI realizing traversal of 7 hops within a cycle at 548 MHz, dissipating 1.57 to 2.53 W. It enables a rigorous understanding of the tradeoffs between router clock frequency, network latency and throughput, and is a demonstration of the proposed synthesis toolchain. The SCORPIO 36-core chip (joint work) is an 11 x 13 mm2 chip in 45 nm SOI demonstrating snoopy coherence on a scalable ordered mesh NoC, with the NoC taking just 19 % of tile power and 10 % of tile area [19, 28].by Chia-Hsin Chen.Ph. D
Distributed mobile platforms and applications for intelligent transportation systems
Get PDFThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 70-75).Smartphones are pervasive, and possess powerful processors, multi-faceted sensing, and multiple radios. However, networked mobile apps still typically use a client-server programming model, sending all shared data queries and uploads through the cellular network, incurring bandwidth consumption and unpredictable latencies. Leveraging the local compute power and device-to-device communications of modern smartphones can mitigate demand on cellular networks and improve response times. This thesis presents two systems towards this vision. First, we present DIPLOMA, which aids developers in achieving this vision by providing a programming layer to easily program a collection of smartphones connected over adhoc wireless. It presents a familiar shared data model to developers, while underneath, it implements a distributed shared memory system that provides coherent relaxed-consistency access to data across different smartphones and addresses the issues that device mobility and unreliable networking pose against consistency and coherence. We evaluated our prototype on 10 Android phones on both 3G (HSPA) and 4G (LTE) networks with a representative location-based photo-sharing service and a synthetic benchmark. We also simulated large scale scenarios up to 160 nodes on the ns-2 network simulator. Compared to a client-server baseline, our system shows response time improvements of 10x over 3G and 2x over 4G. We also observe cellular bandwidth reductions of 96%, comparable energy consumption, and a 95.3% request completion rate with coherent caching. With RoadRunner, we apply our vision to Intelligent Transportation Systems (ITS). RoadRunner implements vehicular congestion control as an in-vehicle smartphone app that judiciously harnesses onboard sensing, local computation, and short-range communications, enabling large-scale traffic congestion control without the need for physical infrastructure, at higher penetration across road networks, and at finer granularity. RoadRunner enforces a quota on the number of cars on a road by requiring vehicles to possess a token for entry. Tokens are circulated and reused among multiple vehicles as they move between regions. We implemented RoadRunner as an Android application, deployed it on 10 vehicles using 4G (LTE), 802.11p DSRC and 802.11n adhoc WiFi, and measured cellular access reductions up to 84%, response time improvements up to 80%, and effectiveness of the system in enforcing congestion control policies. We also simulated large-scale scenarios using actual traffic loop-detector counts from Singapore.by Jason Hao Gao.S.M
Design and implementation of in-network coherence
No full textThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Title as it appears in MIT Commencement Exercises program, June 2013: Design and implementation of in-network coherence. Cataloged from PDF version of thesis.Includes bibliographical references (p. 101-104).CMOS technology scaling has enabled increasing transistor density on chip. At the same time, multi-core processors that provide increased performance, vis-a'-vis power efficiency, have become prevalent in a power constrained environment. The shared memory model is a predominant paradigm in such systems, easing programmability and increasing portability. However with memory being shared by an increasing number of cores, a scalable coherence mechanism is imperative for these systems. Snoopy coherence has been a favored coherence scheme owing to its high performance and simplicity. However there are few viable proposals to extend snoopy coherence to unordered interconnects - specifically, modular packet-switched interconnects that have emerged as a scalable solution to the communication challenges in the CMP era. This thesis proposes a distributed in-network global ordering scheme that enables snoopy coherence on unordered interconnects. The proposed scheme is realized on a two-dimensional mesh interconnection network, referred to as OMNI (Ordered Mesh Network Interconnect). OMNI is an enabling solution for the SCORPIO processor prototype developed at MIT - a 36-core chip multi-processor supporting snoopy coherence, and fabricated in a commercial 45nm technology. OMNI is shown to be effective, reducing runtime by 36% in comparison to directory and Hammer coherence protocol implementations. The OMNI network achieves an operating frequency of 833 MHz post-layout, occupies 10% of the chip area, and consumes less than 100mW of power.by Suvinay Subramanian.S.M
Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
No full textThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.Includes bibliographical references (pages 169-180).Chip Multi-Processors(CMPs) have become mainstream in recent years, providing increased parallelism as core counts scale. While a tiled CMP is widely accepted to be a scalable architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip interconnect directly influences the latency and bandwidth of on-chip cache, scalable interconnect is an essential part of on-chip cache design. On the other hand, optimal design of interconnect can be determined by the traffic forms that it should handle. Thus, on-chip cache organization is inherently interleaved with on-chip interconnect design and vice versa. This dissertation aims to motivate the need for re-organization of on-chip caches to leverage the advancement of on-chip network technology to harness the full potential of future many-core CMPs. Conversely, we argue that on-chip network should also be designed to support specific functionalities required by the on-chip cache. We propose such co-design techniques to offer significant improvement of on-chip cache performance, and thus to provide scalable CMP cache solutions towards future many-core CMPs. The dissertation starts with the problem of remote on-chip cache access latency. Prior locality-aware approaches fundamentally attempt to keep data as close as possible to the requesting cores. In this dissertation, we challenge this design approach by introducing new cache organization that leverages a co-designed on-chip network that allows multi-hop single-cycle traversals. Next, the dissertation moves to cache coherence request ordering. Without built-in ordering capability within the interconnect, cache coherence protocols have to rely on external ordering points. This dissertation proposes a scalable ordered Network-on-Chip which supports ordering of requests for snoopy cache coherence. Lastly, we describe development of a 36-core research prototype chip to demonstrate that the proposed Network-on-Chip enables shared-memory CMPs to be readily scalable to many-core platforms.by Woo Cheol Kwon.Ph. D
The design and implementation of a distributed photo sharing Android application over ad-hoc wireless
Get PDFThesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 51).We present a distributed photo-sharing Android application, CameraDP, that primarily relies on ad-hoc Wifi. The app runs on top of the novel DIstributed Programming Layer Over Mobile Agents (DIPLOMA) programming abstraction. DIPLOMA provides a consistent shared memory over a large distributed system of Android phones. The success rate and latency of photo upload and download on CameraDP were compared to the numbers generated from CameraCL, a 3G or 4G-only version app with the same user interface as CameraDP. Under near-ideal Wifi conditions, a 10- phone CameraDP system yields a 2.8x improvement in latency over a 10 CameraCL phones running on 4G while and a 10.9x improvement over CameraCL running on 3G. The methods and results of this research suggests that distributed ad-hoc Wifi network apps may outperform cellular-network-only apps with improvements in Wifi technology.by HaoQi Li.M.Eng
Replacing cellular with WiFi direct communication for a highly interactive, high bandwidth multiplayer game
Get PDFThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 62-63).The objective of this work is to explore the benefits of replacing cellular with Wi-Fi Direct communication in mobile applications. Cellular connections consume significant power on mobile devices and are too slow for many highly interactive mobile applications. Wi-Fi Direct, the recently released wireless standard, promises to provide the speed, power efficiency, and security of Wi-Fi to devices communicating within a short range. Using Wi-Fi performance as a baseline, the performance of a proof of concept system, Super Tux Kart Direct, is evaluated when communication is enabled by either LTE or Wi-Fi Direct. At the time of writing and to the best of the author's knowledge, Super Tux Kart Direct is the first, real-time, multiplayer kart racing game playable via Wi-Fi Direct.by Pablo Ortiz.S.M
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