102,407 research outputs found
CMOS latch-up failure mode analysis
No full textThe paper describes techniques for the identification of parasitic paths leading to latch-up in CMOS integrated circuits. Several applications of the "Digital Differential Voltage Contrast" to latch-up studies are presente
Latch mechanism
No full textRachet device transfers loads imposed on latch to support structure before latch springs resist loads, positively locks two pivoted structures on contact, and carries loads in all directions
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Strong-back safety latch
No full textThe calculation decides the integrity of the safety latch that will hold the strong-back to the pump during lifting. The safety latch will be welded to the strong-back and will latch to a 1.5-in. dia cantilever rod welded to the pump baseplate. The static and dynamic analysis shows that the safety latch will hold the strong-back to the pump if the friction clamps fail and the pump become free from the strong-back. Thus, the safety latch will meet the requirements of the Lifting and Rigging Manual for under the hook lifting for static loading; it can withstand shock loads from the strong-back falling 0.25 inch
Automatic Gate Latch.
No full textPatent for invention of a gate latch which is very simple, durable and is comparatively inexpensive. This has a swinging latch attached to the gate
Latch.
No full textPatent for a latch for swinging doors, which can be operated from either side of the door
Latch-up DC triggering and holding characteristics of n-well, twin-tub and epitaxial CMOS technologies
No full textThe dependence of the latch-up susceptibility on layout parameters is studied on four stripe structures made using different CMOS processes: a standard n-well, a twin-tub and twin-tub epitaxial technology. The correlation between triggering currents, well and substrate resistances and parasitic transistor gains is studied by means of emitter current triggering measurements and two-dimensional simulations using HFIELDS. Triggering currents higher than 250 mA are obtained on epitaxial structures with n+ guard-rings. Anomalies in triggering and holding electrical characteristics are caused by the three-dimensional distribution of the latch-up current, which is observed by IR microscopy. These anomalies can affect results of conventional latch-up testing method
Gate Latch.
No full textPatent for an automatically releasing latching bolt and other improvements for a gate latch, including illustrations
Gate Latch.
No full textPatent for an improved gate-latch for swinging gates that is especially simple, economic, and efficient
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