1,721,004 research outputs found
Interruzioni Volontarie di Gravidanza: caratteristiche del fenomeno con particolare attenzione alla Sardegna. Stima regionale per le malformazioni cromosomiche e per la Sindrome di Down
Negative pregnancy outcomes by gestational age in Italy. Comparing different international definitions
Dynamic and formal verification of embedded systems: A comparative survey
Embedded Systems, by their nature, constitute a meeting point for communities with extremely different background. In particular, the high demands for quality and reliability for embedded systems have led to complementary quality assurance efforts: hardware engineers have developed techniques for dynamic verification in terms of co-simulation, which, in particular, addresses the different nature of hardware and software components. Thus these techniques are tailored for the transactional level, which comprises dedicated models for the hardware and the software parts. On the other hand, there is a bulk of work on formal verification techniques, which typically address higher levels of abstraction. These techniques are exhaustive in the sense that they cover all the infinite possible paths of their models, however at the price of neglecting many of the low-level aspects treated by co-simulation. It is the goal of this paper to increase the mutual understanding between these communities and to animate research at this exciting borderline
Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing
We present an artificial spiking neuron employing capacitive synapses, that is capable of an adiabatic operation and can achieve a cumulative integration of the input spikes. Our transistor-level circuit simulations show that the neuron can exploit both the charging and recovery phases to drive the membrane potential of the neurons and reach 100-150fJ per synaptic operation with a 99.6%-98.8% efficiency of the adiabatic driving at a 40 kHz resonance
Reducing the spike rate of deep spiking neural networks based on time-encoding
A primary objective of Spiking Neural Networks is a very energy-efficient computation. To achieve this target, a small spike rate is of course very beneficial given the event-driven nature of such a computation. A network that processes information encoded in spike timing can, by its nature, have such a sparse event rate, but, as the network becomes deeper and larger, the spike rate tends to increase without any improvements in the final accuracy. If, on the other hand, a penalty on the excess of spikes is used during the training, the network may shift to a configuration where many neurons are silent, thus affecting the effectiveness of the training itself. In this paper, we present a learning strategy to keep the final spike rate under control by changing the loss function to penalize the spikes generated by neurons after the first ones. Moreover, we also propose a 2-phase training strategy to avoid silent neurons during the training, intended for benchmarks where such an issue can cause the switch off of the network
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches
Traditional implementations of low-power states based on voltage scaling or power gating have been shown to have a beneficial effect on the aging phenomena caused by negative bias temperature instability (NBTI), which can be explained in terms of the intuitive correlation between the idleness and the reduced workload of a system.
Such a joint benefit has been exploited only partially because of the different nature of energy and aging as cost functions: as a performance figure, aging is affected by the worst idleness pattern.
Therefore, large potential energy savings usually result in limited aging reductions.
In this paper, we address this problem in the context of power-managed caches, which represent a critical target for NBTI-reduced aging: given their symmetric structure, SRAM structures are, in particular, sensitive to NBTI effects because they cannot take advantage of the value-dependent recovery typical of NBTI.
We propose a strategy called dynamic indexing, in which the cache indexing function is changed over time in order to uniformly distribute the idleness over all the various power managed units (e.g., lines).
This distribution allows fully using the leakage optimization potential and extending the lifetime of a cache.
We explore various alternatives, in particular different granularities of the power managed units as well as different reindexing functions.
Experimental analysis shows that it is possible to simultaneously reduce leakage power and aging in caches, with minimal power consumption overhead
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