1,721,001 research outputs found
Reducing the Spike Rate in Deep Spiking Neural Networks
No full textOne objective of Spiking Neural Networks is a very efficient computation in terms of energy consumption. To achieve this target, a small spike rate is of course very beneficial since the event-driven nature of such a computation. However, as the network becomes deeper, the spike rate tends to increase without any improvements in the final results. On the other hand, the introduction of a penalty on the excess of spikes can often lead the network to a configuration where many neurons are silent, resulting in a drop of the computational efficacy. In this paper, we propose a learning strategy that keeps the spike rate under control, by (i) changing the loss function to penalize the spikes generated by neurons after the first ones, and by (ii) proposing a two-phase training that avoids silent neurons during the training
Local Area Cloud: a distributed, fault tolerant, and self-configuring architecture for smart home automation
No full textThe thesis deals with the design of a general architecture for SH, which is a very challenging task mainly because of the extremely large variety of devices, link layer technologies, and services that may be involved in such a system. The feasibility of the proposed system architecture has been pragmatically investigated with the development of a novel, distributed, fault tolerant, and self-configuring architecture used for monitoring and controlling home environment through heterogeneous ubiquitous sensor nodes based on a widespread local data collection system, named as Local Area Cloud. By means of this architecture, the system is always aware of the environment status and changes in the system itself are handled during runtime, improving flexibility and making the system independent from external applications. Experimental results show that the system can be successfully employed to address functional and non-functional requirements of smart environments. Furthermore, in order to make the whole system an open source project where developers can contribute by sharing their own applications, it has been implemented an application programming interface (API), which it has been designed to abstract the underlying implementation and only exposing objects and/or actions that developer needs to build their specific service-oriented applications, using the proposed architecture as backbone
Adiabatic leaky integrate and fire neurons with refractory period for ultra low energy neuromorphic computing
Full text linkIn recent years, the in-memory-computing in charge domain has gained significant interest as a promising solution to further enhance the energy efficiency of neuromorphic hardware. In this work, we explore the synergy between the brain-inspired computation and the adiabatic paradigm by presenting an adiabatic Leaky Integrate-and-Fire neuron in 180 nm CMOS technology, that is able to emulate the most important primitives for a valuable neuromorphic computation, such as the accumulation of the incoming input spikes, an exponential leakage of the membrane potential and a tunable refractory period. Differently from previous contributions in the literature, our design can exploit both the charging and recovery phases of the adiabatic operation to ensure a seamless and continuous computation, all the while exchanging energy with the power supply with an efficiency higher than 90% over a wide range of resonance frequencies, and even surpassing 99% for the lowest frequencies. Our simulations unveil a minimum energy per synaptic operation of 470 fJ at a 500 kHz resonance frequency, which yields a 9x energy saving with respect to a non-adiabatic operation
Energy/lifetime cooptimization by cache partitioning with graceful performance degradation
No full textAging of transistors can adversely impact the long-term reliability of devices in subnanometric technologies.
Without any countermeasure, the first component that becomes unreliable will determine the life span of an entire device. The effect is more susceptible in memory arrays, where failure of a single SRAM cell would cause the failure of the whole system.
In this paper, we propose a reliability management technique based on the idea of cache partitioning, which deals with cell failures by gracefully degrading its performance.
By this partitioning-based strategy, various subblocks will become unreliable at different times, and the cache will keep functioning with reduced efficiency.
A coarse-grain implementation of this approach, with the use of a smart aging-driven partitioning algorithm, provides a lifetime extension of more than 2x.
On the other hand, a fine-grain strategy with a single cache line as a unit of power management, stretch the lifetime to its maximum limits with an addition of small hardware overhead
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors
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