1,721,013 research outputs found
Two-Dimensions Vernier Time-to-Digital Converter
No full textA two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches. A 7-bits TDC prototype, targeted for all digital PLL application, was realized in 65 nm CMOS technology with a time resolution of 4.8 ps and a power consumption of 1.65 mW for a conversion rate of 50 Msps. The longest delay line used in such a prototype is one third than what would have been required for a standard Vernier TDC
Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping
No full textA novel class of filters (called pipe filters) that features in-band noise reduction is presented and a current mode biquad cell based on cross-connected cascoded devices is introduced. The presented solution gives in-band high-pass noise shaping and passive pre-filtering of out-of-band blockers. This results in both low in-band noise and high out-of-band IIP3. A 4th-order lowpass prototype in 90 nm CMOS for WCDMA application features 32 μW in-band noise (when integrated over the 2 MHz bandwidth as defined by the standard) and +36 dBm out-of-band IIP3 which results in a 75 dB SFDR with 1.25 mW power consumption. Active die area is 0.5 mm2
3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL
No full textA 3.3 GHz DCO that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The DCO exhibits a phase noise of -127.5 dBc/Hz@1 MHz drawing 16 mA from a 1.8 V supply, resulting in an FoM of 183 dBc/Hz. The active area is 700 ¿m à 450 ¿
"A 2G/3G Cellular Analog Baseband Based on a Filtering ADC"
No full textA current-driven low-pass filter embedded in a sigma-
delta analog-to-digital converter is presented. The implementation
of a class-B feedback digital-to-analog converter, together
with in-band noise reduction and passive filtering, gives the possibility
to handle challenging wireless communication scenarios with
low power consumption. The architecture is a suitable candidate to
implement the entire baseband analog section of a Global System
for Mobile Communications–Universal Mobile Telecommunications
System (GSM–UMTS) reconfigurable receiver
A 2.4 GHz 3.6mW 0.35mm2 quadrature front-end RX for ZigBee and WPAN Applications
No full textIn the design of a single chip for wireless-sensor-network and WPAN applications (e.g., IEEE 802.15.4), the receiver sensitivity is generally sacrificed in favor of a vanishing power consumption and a low-cost solution. There is a trade off between these two requirements, as the use of resonant loads offers high power efficiency while an inductor-free approach saves die area resulting in a cheaper design. Since an LC-oscillator topology is mandatory to achieve a minimal current draw, the reduction of the number of coils has to be done in the LNA, the mixer and the quadrature generator. In this work, starting from the LNA-Mixer and VCO (LMV) cell topology, a single-coil low-power receiver shares the bias current among all the RF blocks of the analog front-end. The receiver prototype chip consumes 3.6mW and has an active die area of 0.35mm2. It is based on a low-IF architecture and includes a baseband variable-gain complex filter for channel selection
A 1.25mW 75dB-SFDR CT filter with in-band noise reduction
No full textIn a direct-conversion wireless receiver the baseband filter should be able to handle large blockers, resulting in a very challenging spurious free dynamic range (SFDR) requirement. In particular, the noise added in-band trades off with the linearity required to handle close out-of-band interferers [1]. Since the integrated noise generally is proportional to kT/C, once the noise floor for the filter is set, the amount of capacitance is roughly defined as well as a lower bound for area and power consumption [2]. The solution presented in this paper aims to break this trade off by inserting an in-band zero in the output noise transfer function to improve the dynamic range
Configurable LNAs in Feedback Common Gate Topology
No full textA unified description of all feedback common gate LNA is presented, providing analytical expressions for gain, noise and linearity for bipolar and CMOS technology. The flexibility of these structures suggests a novel design methodology oriented to configurable low noise amplifiers both in frequency and in performance. Finally two different prototypes tailored for cellular and WLAN receivers are reported
A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer
No full textA low-IF very compact low power quadrature receiver for ZigBee applications is presented. The receiver saves area and power with a quadrature self oscillating mixer based on high Q bond-wire inductors. The prototype, integrated in CMOS 90nm, provides 76dB of maximum voltage gain, with a 10dB noise figure, an IIP3 of -13dBm and a phase noise of 124dBc/Hz LO @ 3.5MHz with an active area of only 0.23mm2 and a power consumption of 3.6mW (including the baseband filter)
Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications
No full textTwo very compact and low power quadrature receivers for ZigBee applications are presented. Area and power savings are obtained through both current reuse and oscillator tank sharing between the I and Q paths. Since this choice can cause I and Q amplitude/phase mismatches, the conversion gain is analyzed and a technique to minimize these errors is implemented. Moreover, since using a single tank makes quadrature generation at the local oscillator level costly and power-hungry, two alternative quadrature generation techniques in the RF path are proposed, together with the corresponding input matching strategies
A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC
No full textA filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. The 90nm CMOS prototype is embedded in a fully integrated tuner compliant with DVB-T and ATSC standards. For a 6MHz channel bandwidth, the filtering ADC exhibits a frequency dependent dynamic range varying from 75.6dB to 90dB while drawing 30mA from a 1.8V supply
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