1,722,119 research outputs found

    An integrated single-stage quasi-resonant power factor correction converter with active clamp circuit

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    A new integrated single-stage zero current switched (ZCS) quasi-resonant converter (QRC) for the power factor correction (PFC) converter is introduced in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of an input current. The proposed converter has the characteristics of the good power factor, low line current harmonics, and tight output regulation. Furthermore, the ringing effect due to the output capacitance of the main switch can be eliminated by use of active clamp circuit. A prototype converter has been designed and experimented based on design equations. The line current waveform of the prototype shows about 15% of total harmonic distortion at rated condition. Also, the efficiency and the power factor can be obtained about 87% and 0.985, respectively, at rated condition. The proposed converter is suitable for a low power level applications with a tightly regulated output voltage and a high switching frequency

    Psychological distress in newly diagnosed patients with gastrointestinal cancer: A scoping review

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    OBJECTIVE: A cancer diagnosis often triggers significant emotional and psychological challenges, underscoring the importance of addressing psychological distress. While psychological distress in patients with gastrointestinal (GI) cancer has been widely studied, less attention has been focused on those who are newly diagnosed. This scoping review aims to map the existing literature on psychological distress in newly diagnosed patients with GI cancer. METHODS: A scoping review was conducted following the framework outlined by Arksey and O'Malley. The last search was carried out on September 23, 2024, across PubMed, CINAHL, EMBASE, Scopus, and PsychINFO for literature published between January 2013 and September 2024. The search terms included "newly diagnosed," "distress," "patients," and "gastrointestinal cancer." A meta-analysis was conducted using the R package to synthesize the prevalence of psychological distress across studies, with a random-effects model applied to account for heterogeneity. RESULTS: Fifteen studies were included in the analysis, revealing an average prevalence of psychological distress of 28.1% (99% CI: 181.84, 433.39). Psychological distress was most prevalent during the diagnostic phase and gradually decreased over time. Factors such as older age, advanced cancer stage, poor performance status, and a lack of social support contributed to increased psychological distress. Additionally, only 20% of the studies were intervention-based. CONCLUSIONS: Approximately one-third of newly diagnosed patients with GI cancer may experience psychological distress. Early identification and intervention to address this distress before treatment initiation are crucial for improving patient outcomes. SYSTEMATIC REVIEW REGISTRATION: osf.io/n2796

    An advanced sustaining technology for plasma display panel using voltage-balancing method

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    A cost-effective plasma display panel (PDP) sustainer employing current injection method (CIM) for energy recovery is proposed. Using a voltage-balancing technique, driver cost can be reduced by about 20%-30% compared with that of the conventional H-bridge driver by using low-voltage switches. The energy recovery performance can be improved by the current that is built up before the energy recovery operation. This buildup current is utilized to change the polarity of the panel electrode and provides additional variable to determine pulse slopes. Experimental results show that the voltage stress of switches connected in series is identically clamped to sustain voltage during sustain operation and that light is emitted more stably by independent control of the rising and falling slopes using CIM. Therefore, the proposed sustainer is expected to be suitable for a low-cost PDP sustaining driver requiring stable discharge characteristics

    Timed compiled-code functional simulation of embedded software for performance analysis of SOC design

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    A new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of input/output (I/O) accesses is crucial to performance estimation and architecture exploration in the timed functional simulation that simulates the whole design at a functional level with timing. A portable compiler is modified to generate time deltas which are the estimated,cycle counts between two adjacent I/O accesses by counting the cycles of the intermediate representation (IR) operations and using a machine description that contains information on a target processor. Since the proposed method is based on the machine-independent IR of a compiler, the method can be applied to various processors by changing the machine description. The experimental results show that the proposed method is effective in that the average estimation error is about 2% and the maximum speed-up over the corresponding instruction-set simulators is about 300 times. The proposed method is also verified in a timed functional simulation environment.This work was supported in part by the Korea Science and Engineering Foundation through the MICROS center and in part by the IC Design Education Center (IDEC). This paper was recommended by Associate Editor R. Camposano

    A single-stage power-factor-correction converter with simple link voltage suppressing circuit (LVSC)

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    A single-stage power-factor-correction ac/dc converter with a simple link voltage suppressing circuit (LVSC) for the universal Line application is proposed. A portion of the energy charged in a boost inductor is directly transferred to a load via LVSC without passing the link capacitor. Using simple circuitry, a low link voltage can be realized without input current deadbands at hue zero crossings, The proposed converter is analyzed and design guidelines for the proper operation of a converter are given. A universal input (90-265-V(rms)) prototype converter with 5-V 12-A output is implemented to verify performance. The experimental results show that the maximum link voltage stress and efficiency are about 447 V and 81%, respectively. The power factor is above 0.96 under the universal line condition when the load is higher than 30%

    EFFECT OF INTERFACIAL DRAG FORCE ON THE NUMERICAL STABILITY OF THE 2-STEP METHOD IN THE 2-FLUID MODEL

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    The stability limit of the implicit Courant-Eulerian (ICE) method was enhanced by adding a stabilization step to the basic ICE method such as the stability enhancing two-step (SETS) method implemented in TRAC-PF1. The matrix size of the SETS method is smaller than that of the fully implicit methods. However, the momentum stabilization steps enlarge the matrix size of the SETS method as the dimension increases. In order to reduce the matrix size of the SETS method in multidimensional problems and to study the effect of the interfacial drag force on stability, a von Neumann stability analysis of the SETS method without momentum stabilization steps (SETS-WM) is presented here. It is found that the interfacial drag force extends the stability limit considerably. When SETS-WM is tested numerically, stability problems have not been encounted when the time step is restricted by the stability limit derived here

    Address code generation for DSP instruction-set architectures

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    This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to the address computation of array accesses. The information is used in generating auto-modification addressing operations provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance and reducing code size
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