1,721,234 research outputs found
Statistical Simulation of Leakage Currents in MOS and Flash Memory Devices with a new multi-Phonon Trap-Assisted Tunneling Model
No full textA new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multi-Phonon Trap-Assisted Tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction
A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling
No full textThis paper presents for the first time a new approach to hot-carrier phenomena leading to an analytical model of both Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) currents. This model can be incorporated in Spice-like models of MOS transistors and Floating Gate (FG) devices to include hot carrier phenomena also in circuit simulations
Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices
No full textThe purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from simulated oxide leakage currents in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/erase cycles, i.e. electrical stress and radiation exposure
Floating Gate devices: operation and compact modeling
No full textThis paper describes a possible approach to Compact Modeling of Floating Gate devices. Floating Gate devices are the basic building blocks of Semiconductor Nonvolatile Memories (EPROM, EEPROM, Flash). Among these, Flash are the most innovative and complex devices. The strategy followed developing this new model allows to cover a wide range of simulation conditions, making it very appealing for device physicists and circuit designers
Statistical simulations for flash memory reliability analysis and prediction
No full textIn this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual Flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art Flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V-T) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on Flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements
Statistical simulations to inspect and predict data retention and program disturbs in Flash memories
No full textA new statistical model of stress-induced leakage current (SILC) is implemented and used to predict data retention and program disturbs of state-of-the-art flash memories, and to correlate oxide characterization outputs (density, cross section, energy level of defects) to flash memory reliability. Physical mechanisms inducing the largest threshold voltage (VT) degradation are explained, and tunnel oxide scaling effects on flash reliability are predicted
Gate current in ultrathin MOS capacitors: a new model of tunnel current
No full textWe have deduced the analytical expression of the tunneling current across a thin oxide layer for a MOS capacitor, by introducing a new double-box simplified model of the oxide layer. We have developed this model to study some characteristics of the tunneling current, which are neglected when the usual Fowler-Nordheim description is adopted. Matching between experimental and simulated curves is excellent, and no free parameter is needed to adjust the fitting quality, once the values of the main physical parameters are chosen. The model quantitatively describes the quantum oscillations of the gate current produced by the interference between the coherent incident electron-wave and the electron-wave reflected at the oxide/anode interface, From the period of the quantum oscillations, we have deduced a semiempirical relation useful to evaluate the oxide thickness. The quantum oscillations amplitude is related to the oxide/anode interface roughness, which is accounted for by a rugosity parameter introduced in our model. The temperature dependence of the tunneling current has been taken into account as well in two parameters of the model
Modeling strategies for flash memory devices
No full textIn this paper, we will review the modeling strategies for standard and advanced Flash memory devices based on Floating Gate devices developed by our research group in the last ten years. We will show a complete compact model that includes program/erase and leakage currents that can be used to simulate memory cells in both DC (read operation) and transient conditions (Program/Erase). The same model can be used also for reliability simulations by providing good descriptions of the degradation mechanisms. We will also show the extended model for circuit simulation of NAND strings, modified to account for capacitive coupling effects. Finally, we will show how the same framework can be used to develop a compact model for operations of advanced planar charge-trapping memory devices
Profiling charge distribution in NROM devices
No full textNROM memory cells are proposed as one of the most promising non-volatile memories. Issues on scaling and endurance have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge trapping material. Therefore, a deeper analysis of the injected-charge distribution region is very important for program/erase bias optimization, reliability prediction and future scaling. In this paper, we introduce and discuss two tools, based on subthreshold slope and temperature effects, able to correctly estimate program charge distribution features from simple ID - VGS measurement
Defect spectroscopy and engineering for nanoscale electron device applications: A novel simulation-based methodology
No full textIn this work we present a novel simulation-based methodology for the defect spectroscopy in dielectric materials. The cross-correlated simulation of electrical characteristics (IV, CV, GV, BTI, charge pumping and noise) is exploited to profile the properties and energy-space distribution of the defects within the oxide bandgap. This novel defect spectroscopy technique will be applied to three case studies, i.e. Si- MOSFET gate stack optimization with either Si and beyond Si channel (InGaAs), and STO MIM DRAM capacitor scaling. The integration of these methods into the process optimization will lead to a strong reduction of the time/cost required for the development of novel device architectures
- …
