513 research outputs found
U.Galvanetto, L. Monopoli, C. Surace, A. Tassotti Experimental Application of a DamageLocalisation Technique Based on Smoothed Proper Orthogonal Modes
A Method for the Parameter Identification of an AC Motor High-Frequency Model Based on the Exchange Market Algorithm
The use of wide bandgap semiconductor devices, such as SiC and GaN MOSFETs, in high-frequency converters introduces new challenges for the design of electric drives. The very fast switching transient of which these devices are capable, in fact, can become a serious threat for the reliability of the entire system. Electromagnetic interferences due to the high dv/dt and di/dt, voltage reflections along the cable that cause overvoltage and ringing at the motor terminals, and large common-mode voltages that produce current circulation in the motor bearings are recognized as the major phenomena leading to premature failure of the drive. It is therefore important for designers to approach the problem from a system point of view, having the possibility to accurately model the system in the high frequency domain to take appropriate measures to increase reliability. In this paper, an automated fitting procedure is proposed to identify one of the most accurate high-frequency models of an induction machine. The procedure relies on the experimental measurement of the differential, common-mode and parasitic impedance of the tested machine and adopts Exchange Market optimization algorithm to search for the best approximation of the three measured impedances. Implementation issues and advantages are presented and discussed
Self-Consumption Optimization in an Energy Community
In recent years, a fast penetration of renewable sources in power electrical systems is taking place, providing many benefits; indeed, thanks to the Energy Community development, there is the possibility that renewable energy generated by a user can be shared by the other users of the community too. However, to make this happen, power electronics converters are the main characters of a proper management of shared energy. In this paper authors propose a Simulink scheme of an Energy Community, in which converters and related control systems have been modelled. Through the Maximum Power Point Tracking control of the photovoltaic converter, the maximum photovoltaic power is extracted, and through the double-loop control of the grid-connected inverter, only active power is fed into the grid, generating a current in phase with the grid voltage. The major innovation introduced in this paper is the modelling of a power sharing supervisor system that coordinates all the bidirectional converters which interface batteries to the community, according to their states of charge, in order to set power exchanges with the grid to zero. Results obtained from simulations demonstrate that, by varying load, photovoltaic production and batteries states of charge, the self-consumption optimization aim is pursued
READ poster: Paula Monopoli
Professor Paula Monopoli recommends In the Interests of Justice: Reforming the Legal Profession by Deborah L. Rhode, and Women & Leadership ed. By Barbara Kellerman and Deborah L. Rhode.https://digitalcommons.law.umaryland.edu/read/1014/thumbnail.jp
DSCC Converter as Energy Router for Rural Energy Communities: a Case Study Under Vertical Imbalance
The sustainable electrification of rural communities relies on the effective utilization and integration of renewable energy sources, which are generally connected to the grid using multiple independent converters. In contrast, the adoption of a single centralized multiport converter acting as energy router can help to reduce operation costs, to increase power density, and to simplify energy management and maintenance, offering a more efficient solution compared to multiple converters. This paper investigates the use of modular multilevel converters acting as a multiport energy router to connect various energy sources to the grid. In this scenario, a vertical imbalance in the arm voltages of the converter, due to the different operation patterns of the connected sources, can harm the stability of the converter. The system's internal dynamics can be leveraged as a control mechanism to ensure system functionality and to prevent unequal stress on semiconductor devices within the individual cells. A case study involving vertical imbalance is analyzed in this paper to assess the converter's potential to improve the reliability and efficiency of renewable energy integration in rural electrification projects
Improving Rural Microgrid Performance with SiC MOSFET-Based Three-Phase Inverters
Microgrids represent a fundamental solution for the electrification of rural communities, providing clean energy through renewable resources. This article explores the importance of integrating SiC MOSFET based three-phase inverters. These new generation transistors are known for their good electrical and thermal characteristics, guaranteeing significant advantages in terms of energy efficiency, thermal management, and operational reliability, making them ideal for high-power and high-frequency applications. The research focuses on the design, analysis, and future modeling of a three-phase inverter, whose results demonstrate an improvement in its performance with a significant reduction in losses compared to those that would occur with the use of a traditional silicon transistor. Furthermore, a suggestion is made on the possible construction of a thermal model, which would allow the simulation of the inverter for the optimization of the entire microgrid. The results highlight how the use of SiC MOSFETs can improve the performance of microgrids, supporting the electrification of rural areas with sustainable energy solutions
ST-segment elevation myocardial infarction with concomitant multiple coronary arteries thromboses in a young patient with hyperhomocysteinaemia
ST-segment elevation myocardial infarction with concomitant multiple coronary arteries thromboses in a young patient with hyperhomocysteinaemi
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
The rapid development of Artificial Intelligence (AI) algorithms has created a need for a resource-optimised hardware accelerator. Among various platforms, Coarse-Grained Reconfigurable Array (CGRA) have gained importance as on-edge accelerators. They comprise of heterogeneous Processing Element (PE) matrix, which allows for high flexibility and parallelisation of calculations. They are mainly used for speeding up Data Flow Graph (DFG) execution. We aim to provide a general purpose, highly parameterised, and flexible architecture for AI on-edge data crunching. We propose a CGRA with a vector extension which allows for dynamically adjustable precision of calculation while maintaining a desired performance-power-area optimisation. It targets 4 bits integer (INT4) and 8 bits integer (INT8) quantization for fast and efficient Neural Network (NN) processing. In this paper, we examined hardware costs required to support the vector extension functionality. We synthesised the design on the 40nm Standard-Cell technology from TSMC. The obtained results show that the proposed extension attains on average 28.2% decrease in power consumption and 21.6% decrease in area compared to a reference design of the same computation power
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications
Artificial Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhead, power consumption, and fault-tolerant solutions. In this particular scenario, soft General-Purpose Computing on Graphic Processing Units has the potential to revolutionise space-related activities. Indeed, by leveraging both Field Programmable Gate Array technology and Graphic Processing Unit computing, it becomes feasible to achieve high-performance capabilities without compromising neither power consumption nor radiation tolerance features. Moreover, the use of reconfigurable hardware can facilitate the acceleration of a wide range of Machine Learning algorithms, avoiding the drawbacks of excessive specialisation. This paper explores the State-of-the-Art in terms of hardware platforms for on-the-edge acceleration of Artificial Intelligence algorithms and compares it with a possible System-on-Chip implementation based on a soft-Graphic Processing Unit. Then, the attention is shifted towards the investigation of key aspects for future space missions, such as reliability and Dynamic Partial Reconfiguration. We point out the lack of European technological solutions, emphasising the promising potential offered by NanoXplore devices. We also discuss the importance of fault detection and mitigation techniques in space applications, covering the most commonly employed hardware methods for reliability enhancement and highlighting the lack of work in the field of General-Purpose Computing for Graphic Processing Units, especially in the space sector. Furthermore, we briefly examine the implementation of Dynamic Partial Reconfiguration over a System-on-Chip featuring a soft-Graphic Processing Unit IP. Finally, in the last section of the paper, we hint at future development of the project and conclude the work
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip
For many years, General Purpose Computing on Graphic Processing Units has been widely exploited in different fields of application. The hardware architectures enabling this kind of computation are increasingly complex, and their use for on-the-edge applications is often constrained by the limited resources that characterise the systems involved. As such, implementing Graphic Processing Units as soft architectures on Field Programmable Gate Arrays could permit to tune their size, performance and resource usage accordingly to the application requirements. Exploiting the so-called Dynamic Partial Reconfiguration technology can allow specialisation of part of the system architecture, creating heterogeneous computing systems with better resource utilisation and lower power consumption. In this work, we describe the implementation on Field Programmable Gate Arrays of a System-on-Chip featuring a soft-Graphic Processing Unit, whose size and performance have been tuned by means of Partial Reconfiguration. Considering the Sobel Filter as a reference kernel, we discuss some results for reconfiguration time and throughput. Furthermore, we identify the minimum task sizes for which initiating the reconfiguration process gives an advantage in terms of execution time
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