25 research outputs found
Energy-aware system-on-chip for 5 GHz wireless LANs
No full textThis paper presents the realization of an energy-aware system-on-chip that implements the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also covers critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral inter-faces were carefully combined and optimized for the targeted application, leading to a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 μm CMOS pro-cess and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications
No full textA simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
No full textWe present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results
The impact of cognitive behavioural therapy for insomnia on objective sleep parameters: A meta-analysis and systematic review
No full textIt is well-established that cognitive behavioural therapy for insomnia (CBT-I) improves self-reported sleep disturbance, however the impact on objective sleep is less clear. This meta-analysis aimed to quantify the impact of multi-component CBT-I on objective measures of sleep, indexed via polysomnography (PSG) and actigraphy. Fifteen studies met inclusion criteria. Following appraisal for risk of bias, extracted data were meta-analysed using random-effects models. The quality of the literature was generally high, although reporting of methodological detail varied markedly between studies. Meta-analyses found no evidence that CBT-I reliably improves PSG-defined sleep parameters. Actigraphy evidence was more mixed; with a small effect for reduction in sleep onset latency (Hedge's g = −0.28 [95% confidence interval (CI) −0.51 to −0.05], p = 0.018) and a moderate effect for reduction in total sleep time (TST) (Hedge's g = −0.51 [95% CI −0.75 to −0.26], p < 0.001). In contrast, and consistent with recent meta-analyses, CBT-I was associated with robust improvements in diary measures of sleep initiation and maintenance (Hedge's g range = 0.50 to 0.79) but not TST. While the literature is small and still developing, the sleep benefits of CBT-I are more clearly expressed in the subjective versus objective domain
Modeling the dynamic behavior of series-connected MOSFETs for delay analysis of multiple-input CMOS gates
No full text
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices
No full textIn this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results to accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations
