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    VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

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    This work was supported in part by the Swiss NSF ML-Edge Project under Grant Agreement (GA) no. 200020_182009, in part by the ReSoRT Project funded by Botnar Foundation under GA no. REG-19-019, in part by the ERC Consolidator Grant COM-PUSAPIEN under GA no. 725657, and in part by a joint research grant for ESL-EPFL by IMEC
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