42 research outputs found
Clock multiplication techniques for high-speed I/Os
No full textGeneration of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored.
First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.
Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB.
Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01The student, Romesh Kumar Nandwana, accepted the attached license on 2017-04-17 at 15:09.The student, Romesh Kumar Nandwana, submitted this Dissertation for approval on 2017-04-17 at 15:42.This Dissertation was approved for publication on 2017-04-19 at 08:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #10816 on 2017-08-10 at 15:05:48Made available in DSpace on 2017-08-10T20:32:59Z (GMT). No. of bitstreams: 3
NANDWANA-DISSERTATION-2017.pdf: 11016809 bytes, checksum: 1b5e34fe2c8986eeef6902237bb6f311 (MD5)
LICENSE.txt: 4218 bytes, checksum: a246f466819d5f63b537a54ce4202fa9 (MD5)
PROQUEST_LICENSE.txt: 4564 bytes, checksum: 451c495ff0b82c7566e4aac529f530bf (MD5)
Previous issue date: 2017-04-19Embargo set by: Colleen Fallaw for item 102771
Lift date: 2019-08-10T21:27:21Z
Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 102771 on 2019-08-11T09:15:10Z
Effect of Surface Treatments on Tensile and Flexural Properties of Carbon Fiber Reinforced Friction Material
No full textFinite element analysis on prosthetic leg under different loads and flexion angles for medical applications
No full textProsthetic legs are mainly used to perform leg amputations more easily and sometimes the appearance is similar to a real leg. Different types of legs have been developed in recent days to be used in specific fields like running, cycling in sports and normal walking. The selection of materials and load bearing capacity of a leg determines its usage for any field of application. The behavior of prosthetic legs can be assessed properly by performing a finite element analysis on it with varying material properties and loads before it undergoes a designing and manufacturing stage. In the current study, Al alloy, Ti alloy, unidirectional Carbon fiber epoxy (UDCFE) and combined composite material which include (CF, UDCFE and Ti alloy) are used as materials for the prosthetic leg. A prosthetic leg model of C Type with its main parts being the sleeve, the rod and the base foot was designed initially by using the Solid Works 2010 software and the assembled file was imported to Ansys Workbench 2020 to perform a static and fatigue analysis. The static analysis was performed under four different load conditions, i.e. 60 kg, 70 kg, 80 kg and 90 kg, considering the different human weights of the body. A fatigue analysis was done by using the Soderberg method and applying a sinusoidal varying load for low cycle fatigue conditions. Theoretical calculations were also performed at various inclinations of foot 10°, 20°, and 30° with the ground and stresses were evaluated using finite element equations. The results obtained theoretically were compared with the analytical results. The best material which provided the lesser value of deformation and sustaining more loads with a lower value of the damage factor was selected for the design. Further experimental studies were suggested based on the results obtained from this work
Analysis on two wheeler chassis frame of e-bike subjected to static and impact loads
No full textThe future of automotive industry is to design and develop electrical vehicles to control the emissions released from gaseous fuels and not to release any harmful gases in to atmosphere. In this work, an attempt was made to analyze the behavior of two wheeler E- bike with alternative materials of frame such as Aluminum alloy (Al-A), Titanium alloy (Ti-A), Grey cast iron (G-CI), Carbon fiber epoxy (CF-E), and Structural steel (ST-S) and compared with AISI-1020 material. The frame of Yamaha R15 is initially modeled by using solid work and imported to Ansys. Static analysis was performed by applying a load of 1500 N on the frame and Impact analysis was performed by applying velocity of 27.7 m/s along X direction. The values of equivalent von Mises stress and total deformation for all the materials are observed. After performing static analysis, it was observed that, CF- Epoxy material exhibited higher value of Equivalent von Mises stress (7.659*107 Pa) and lower total deformation of (0.304×10-6 mm) compared to remaining materials. Based on impact analysis , it was observed that, CF-E exhibited better von Mises stress of (3994.9 MPa) closer to AISI 1020 and structural steel materials and total deformation is observed to be lower value (0.1106 mm) compared to remaining materials
Energy-efficient wireline transceivers
No full textPower-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50.The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42.This Dissertation was approved for publication on 2016-09-30 at 13:20.DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3
SHU-DISSERTATION-2016.pdf: 13625828 bytes, checksum: 6f7a554d7374c812e5874362c8a3664a (MD5)
LICENSE.txt: 4209 bytes, checksum: 9364f41c0fe9c8f540827190943f3d0f (MD5)
PROQUEST_LICENSE.txt: 4555 bytes, checksum: a4c0059f8ce4019ea372f3a0c69ce926 (MD5)
Previous issue date: 2016-09-30Embargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:02:22Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:03:32Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:05:02Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:06:55Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 98665 on 2019-03-02T10:15:18Z
Women’s Entrepreneurship in Patriarchal Societies: The Case of Women’s Cooperatives in Turkey
No full textThis chapter explores the limits of and prospects for women’s entrepreneurship in patriarchal communities. The chapter investigates the patriarchal institutions and societal norms which work against women’s entrepreneurial activities and women’s presence in socioeconomic life in general. It also delves into women’s strategies to bargain, deal, and cope with patriarchal norms and institutions. The research is based on an extensive fieldwork on the case of Turkey, a country replete with patriarchal norms and institutions. The author conducts in-depth semi-structured interviews with members of women’s cooperatives throughout Turkey to better understand and explain the obstacles against women’s entrepreneurship in patriarchal societies and how women deal with these obstacles in their daily, entrepreneurial practices. In light of the fieldwork findings, the chapter concludes with policy implications and recommendations for more egalitarian and prosperous societies
Design of energy efficient high speed I/O interfaces
No full textThe student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs.
A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.
Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers.
We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01The student, Mrunmay Vyankatesh Talegaonkar, submitted this Dissertation for approval on 2016-03-11 at 14:46.This Dissertation was approved for publication on 2016-03-15 at 08:51.DSpace SAF Submission Ingestion Package generated from Vireo submission #9102 on 2016-07-07 at 14:16:14Made available in DSpace on 2016-07-07T21:14:23Z (GMT). No. of bitstreams: 3
TALEGAONKAR-DISSERTATION-2016.pdf: 8364009 bytes, checksum: 6e6c0881b97d27efba82d3d57944a59b (MD5)
LICENSE.txt: 4227 bytes, checksum: 16fa7e36a1560619e87972302c99bbd0 (MD5)
PROQUEST_LICENSE.txt: 4573 bytes, checksum: 06dca634fff396b5397a0184d0ca556c (MD5)
Previous issue date: 2016-03-15Embargo set by: Seth Robbins for item 93225
Lift date: 2018-07-07T21:14:52Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 93225
Lift date: 2018-07-07T21:18:16Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 93225 on 2018-07-08T09:15:16Z
Challenges in introducing ceramic fiber and other hybrid reinforcements in friction materials
No full textIn this study, an attempt was made to develop a high strength thermal resistant friction material using ceramic fiber as the main fiber and varying the wollastonite content. In addition to the ceramic fiber, 19 various ingredients were considered as fibers, frictional additives and fillers for improving the performance of the composite. The main challenge is to develop a friction material capable of withstanding dynamic loads and severe temperatures encountered during braking. Three friction materials (CERA-I, CERA-II, and CERA-III) were fabricated using a hot press method. After fabrication, the samples were evaluated for physical and mechanical properties. The actual performance was predicted using a friction test rig equipment. The tests were carried at pressures of 30 MPa and 15 MPa under a speed of 600 rpm. The materials were characterized using Scanning electron microscope (SEM), EDXA, porosity and thermo-gravimetric analysis (TGA) for determination of distribution of ingredients and chemicals present in the composite. The results revealed that, inclusion of ceramic fiber with other ingredients possess superior properties in terms of mechanical, physical and wear properties. Out of these three samples, CERA-III friction material exhibited better performance compared to the remaining samples
