78 research outputs found
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling
No full textA 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.Accepted Author ManuscriptMicroelectronic
Tissue- or neurostimulator
No full textTissue- or neurostimulator, comprising a power supply (Vdd) and an implantable pulse generator (IPG) powered by said power supply (Vdd) to which an electrode or electrodes are connected or connectable for delivery of pulses from the pulse generator to a patient's region of interest or tissue so as to provide said region of interest or tissue with electrical stimulation, which pulse generator comprises a switching cir- cuit providing an intermittent connection with the electrode or electrodes, wherein the pulse generator comprises at least one inductor (L) for storing of energy from the power supply (Vdd) and subsequent release to the patient's region of inter- est or tissue through the electrode or electrodes.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc
Buck converter for on-chip reference generation
No full text2010 Summer.Includes bibliographical references (pages 83-85).Most modern day chips use an on chip voltage reference, also known as a bandgap voltage reference generator, to provide a stable reference, independent of power supply voltage (VDD) ripples and compensated for temperature variations. When power supply voltage decreases as the process feature size (gate length) decreases, it imposes challenges in terms of headroom and other factors to achieve a stable bandgap voltage reference. It also needs to be scaled down to VDD/2 for practical uses and provide a common mode voltage of VDD/2 of on-chip circuits. This thesis discusses a buck converter which uses an alternative to pulse width modulation (PWM) for stable reference generation and directly generates a VDD/2 reference using a novel inductor ripple current cancellation technique, which cancels inductor ripple current and therefore does not require a large capacitance for filtering of inductor ripple. An alternative to the pulse width modulation (PWM) technique is proposed, which uses common mode bias and transconductance (gm) tuning to keep the reference output constant for variable loads, and a temperature compensation techniques is used to minimize temperature sensitivity
A Highly Linear Wideband Polar Class-E CMOS Digital Doherty Power Amplifier
No full textThis article presents the first application of a digital-intensive intrinsically linear digitally controlled class-E technique in a Doherty configuration. By careful nonlinear segmentation and multiphase RF-clocking along with overdrive-voltage control and automatic duty-cycle correction, it is shown that even the nonlinearities related to Doherty operation can be fully handled by the underlying design such that digital predistorion (DPD) can be, in principle, omitted. The nonlinearity behavior of the whole digital Doherty power amplifier (PA) is analyzed, and closed-form equations are given to predict the AM-AM and AM-phase modulation (PM) curves. In addition, time/phase mismatch between the peak and main branches and the AM and PM signals is accurately compensated. In order to achieve the maximum intrinsic linearity, two separate chips with the same architecture, but different design parameters, are fabricated as the main and peak amplifiers in 40-nm bulk CMOS. To achieve a large RF bandwidth and high passive combiner efficiency, a differential low-loss, wideband Marchand balun-based Doherty power combiner, implemented using reentrant coupled lines with independent second-harmonic control is proposed, and together with the matching network is fabricated on a two-layer PCB. The measured peak/6-dB power backoff P OUT, drain efficiency/power-added efficiency at 2.4 GHz are 17.5 dBm/12.2 dBm, 57%/52% and 36%/25% with VDD main/peak = 0.6 V/0.7 V. Measured results without using DPD show -41-dBc adjacent channel power ratio (ACPR) and -36-dB error vector magnitude (EVM) for a 16-MHz OFDM signal at 2.5 GHz. By using DPD, the measured ACPR and EVM of a 16-MHz/32-MHz OFDM signals are -52 dBc/-48 dBc and -50 dB/-48 dB, respectively.Accepted author manuscriptElectronic
Value-driven rotorcraft design through integrated product/process development and robust design simulation
No full textIn his 1999 AHS Nikolsky Lecture: Technology for Rotorcraft Affordability through Integrated Product/Process Development (IPPD)[1] the author described the cultural change taking place in industry and government due to the Quality Revolutionwhich identified the need for concurrent engineering education and training[2],as well as new systems approach methodologies that captured the essence of IPPD and Product/Process Simulation. Something like a modern approach to the systems engineering methodology that was developed in the late 1950's and early 1960's for designing and building large scale complex systems, such as ballistic missiles and manned space flight systems, was needed. A generic IPPD methodology was developed by the primary author and his colleagues and taught to industry and government through short courses and professional education. This generic IPPD methodology also became the foundation for the development of the Georgia Tech graduate program in Aerospace Systems Design education and research and led to a large, unique laboratory, the Aerospace Systems Design Laboratory (ASDL), established in 1992, which is now believed to be the largest graduate university complex system design laboratory in the world. With research grants from government and industry the generic IPPD methodology was expanded to include Robust Design Simulation (RDS), Fast Probability Integration (FPI) and Technology Identification Evaluation & Selection (TIES).[1] A summary of this evolution to RDS and some of the PhD research that led to this evolution has been documented in Value-Driven Design (VDD)[3]. VDD has been at the heart of the IPPD through RDS methodology. This paper will describe how VDD has been applied for numerous rotorcraft designs through the AHS and rotorcraft industry student design competitions. It will also describe planned research efforts to expand VDD to Value Based Acquisition (VBA) to help make Future Vertical Lift (FVL) more capable, available, dependable and affordable
Negator-based Switch Capacitor Buck-boost DC-DC Converter
No full textThe development of the Internet of Things has given rise to enormous new industries and applications, including automobiles, smart healthcare systems, smart houses, etc, and the power supply has become the major constraint preventing them from further increasing logic speed. Thus, a SC(switch-capacitance) DC-DC converter with high efficiency, integration on-chip, and multiple voltage conversion ratio (VCRs) is significantly important.SAR(successive Approximation Register) SC was published in 2013, it realized 2n − 1 voltage conversion ratios with n 2:1 SC stage with the cost of charge sharing loss. In 2014, Recursive topology minimized charge-sharing loss by maximizing the connection to the power rail to improve efficiency. While both topologies only offer 7 VCRs for 3 stages, the new topology utilizing the voltage negative feedback technique has expanded this range to 79 ratios, including all p/q rational ratios from 1/2 to 15/16.Each ratio is written in the form Vout=A ∗ VDD − B ∗ Vout, and only three voltage negative feedback module(negators) are to be used :VDD −Vout,2VDD −Vout,−Vout.This paper presents an improved design to expand this VCR range to boost operation, achieving VCR from 15/16 to 16 times the input.In total,3 2:1 SC stages and 3 negators are applied, with a total capacitance of 1.3nF. Thecapacitance of 3 stages and negators are 130p,260p,520p, and 130p respectively. The systemwas designed and fabricated in a 180-nm BCD process, the peak efficiency is achieved at a 2:1ratio @20MHz, with an efficiency of 82.28%, reached load current =6.4mA. The layout area isapproximately 2.084mm2 , and the current density estimated is 3.07 mW/mm2. The design has remarkably expanded the 79 VCR options to both buck operation and boost operationElectrical Engineerin
New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications
No full textEnergy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method; (2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated; (3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under Vdd=199mV and Vdd=145mV, targeting energy-efficiency priority and Vdd priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design
Implantation of a single-lead atrioventricular synchronous (VDD) pacemaker in a dog with naturally occurring 3rd-degree atrioventricular block
No full textLR: 20061115; PUBM: Print; JID: 8708660; ppublishSource type: Electronic(1
Vitamin D prevents articular cartilage erosion by regulating collagen II turnover through TGF-beta 1 in ovariectomized rats
No full textObjective: To explore the effect of vitamin D on turnover of articular cartilage with ovariectomy (OVX) induced OA, and to investigate transforming growth factor-beta 1 (TGF-beta 1) as a possible underlying mechanism mediated by 1 alpha,25(OH)(2)D-3. Design: Sixty-six rats were randomly allocated into seven groups: sham plus control diet (SHAM+CTL), OVX+CTL diet, sham plus vitamin D-deficient (VDD) diet, OVX+VDD diet, and three groups of ovariectomized rats treated with different doses of 1 alpha,25(OH)(2)D-3. The cartilage erosion and the levels of serum 17 beta-estradiol, 1 alpha,25(OH)(2)D-3 and C-telopeptide of type II collagen (CTX-II) were measured. TGF-beta 1, type II Collagen (CII), matrix metalloproteinases (MMP)-9,-13 in articular cartilage were assessed by immunohistochemistry. TGF-beta 1 and CTX-II expression were measured in articular cartilage chondrocytes treated with/without tumor necrosis factor (TNF-alpha), 1 alpha,25(OH)(2)D-3, and TGF-beta receptor inhibitor (SB505124) in vitro. Results: Cartilage erosion due to OVX was significantly reduced in a dose-dependent manner by 1 alpha,25(OH)(2)D-3 supplementation, and exacerbated by VDD. The expressions of TGF-beta 1 and CII in articular cartilage were suppressed by OVX and VDD, and rescued by 1 alpha,25(OH)(2)D-3 supplementation. The expression of MMP-9,-13 in articular cartilage increased with OVX and VDD, and decreased with 1 alpha,25(OH)(2)D-3 supplementation. In vitro experiments showed that 1 alpha,25(OH)(2)D-3 increased the TGF-beta 1 expression of TNF-alpha stimulated chondrocytes in a dose-dependent manner. 1 alpha,25(OH)(2)D-3 significantly counteracted the increased CTX-II release due to TNF-alpha stimulation, and this effect was significantly suppressed by SB505124. Conclusion: VDD aggravated cartilage erosion, and 1 alpha,25(OH)(2)D-3 supplementation showed protective effects in OVX-induced OA partly through the TGF-beta 1 pathway. (C) 2015 Osteoarthritis Research Society International. Published by Elsevier Ltd. All rights reserved.National Natural Science Foundation of China [11472017, 11002004]; Beijing New-star Plan of Science and Technology [2010B003]SCI(E)[email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency
No full textNetworks-on-Chip (NoCs) are prone to within-die process variation as they
span the whole chip. To tolerate variation, their voltages (Vdd) carry overprovisioned
guardbands. As a result, prior work has proposed to save energy
by dynamically managing Vdd, operating at reduced Vdd while occasionally
su ering and xing errors. Unfortunately, these proposals use ad-hoc controller
designs that may not work under other scenarios and do not provide
error bounds.
This thesis develops a scheme that dynamically minimizes the Vdd of groups
of routers in a variation-prone NoC using formal control-theory methods.
The scheme, called Contra, saves substantial energy while guaranteeing the
stability and convergence of error rates. Moreover, the scheme is enhanced
with a low-cost secondary network that retransmits erroneous packets for
higher energy e ciency. The enhanced scheme is called Contra+. Both
Contra and Contra+ are evaluated using simulations of NoCs with 64{100
routers. In an NoC with 8 routers per Vdd domain, the proposed schemes
reduce the average energy consumption of the NoC by 27%; in a futuristic
NoC with one router per Vdd domain, Contra+ and Contra reduce the average
energy consumption by 37% and 32%, respectively. The performance impact
is negligible. These savings are signi cant over the state-of-the-art. The
results categorically state that formal control is essential to attain a stable,
scalable, and energy-efficient design. Additionally, it is found that while the
secondary network helps Contra+ attain higher energy savings, it has a nonnegligible
hardware cost. Hence, Contra is the most cost-effective design.Item withdrawn by Laura Spradlin ([email protected]) on 2014-12-05T17:11:52Z
Item was in collections:
University of Illinois Theses & Dissertations (ID: 1)
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