202 research outputs found
Hyojun dai toa bunzu. 18 , Hawai shoto hen /
No full textMap of Hawaii published in Japan in 1943.; Also available in an electronic version via the internet at: http://nla.gov.au/nla.map-vn6451628. 880-04 Inset: Shinjuwan oyobi Honoruru fukin -- Hawai shoto fukin (Sandoicchi shoto). Scale 1:9,000,000.880-04 Inset: 1-MO!KB'IC!5#i%[i%Ni%ki%k!0o
No full textCreating novel views from a single image has achieved tremendous strides with advanced autoregressive models, as unseen regions have to be inferred from the visible scene contents. Although recent methods generate high-quality novel views, synthesizing with only one explicit or implicit 3D geometry has a trade-off between two objectives that we call the "seesaw" problem: 1) preserving reprojected contents and 2) completing realistic out-of-view regions. Also, autoregressive models require a considerable computational cost. In this paper, we propose a single-image view synthesis framework for mitigating the seesaw problem while utilizing an efficient non-autoregressive model. Motivated by the characteristics that explicit methods well preserve reprojected pixels and implicit methods complete realistic out-of-view regions, we introduce a loss function to complement two renderers. Our loss function promotes that explicit features improve the reprojected area of implicit features and implicit features improve the out-of-view area of explicit features. With the proposed architecture and loss function, we can alleviate the seesaw problem, outperforming autoregressive-based state-of-the-art methods and generating an image approximate to 100 times faster. We validate the efficiency and effectiveness of our method with experiments on RealEstate10 K and ACID datasets.
Rethinking Training Schedules For Verifiably Robust Networks
No full textNew and stronger adversarial attacks can threaten existing defenses. This possibility highlights the importance of certified defense methods that train deep neural networks with verifiably robust guarantees. A range of certified defense methods has been proposed to train neural networks with verifiably robustness guarantees, among which Interval Bound Propagation (IBP) and CROWN-IBP have been demonstrated to be the most effective. However, we observe that CROWN-IBP and IBP are suffering from Low Epsilon Overfitting (LEO), a problem arising from their training schedule that increases the input perturbation bound. We show that LEO can yield poor results even for a simple linear classifier. We also investigate the evidence of LEO from experiments under conditions of worsening LEO. Based on these observations, we propose a new training strategy, BatchMix, which mixes various input perturbation bounds in a mini-batch to alleviate the LEO problem. Experimental results on MNIST and CIFAR10 datasets show that BatchMix can make the performance of IBP and CROWN-IBP better by mitigating LEO
19.6 A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and −56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS
No full text보안된 UAV 통신을 위한 로봇 운영 체제 프레임워크
No full textTo perform advanced operations with unmanned aerial vehicles (UAVs), it is crucial that components other than the existing ones such as flight controller, network devices, and GCS are used. The feature of obstacle avoidance is added to the pre-existing simple waypoint missions to ensure the commercialization of UAVs. However, this feature requires additional hardware and software to recognize obstacles based on radar or lidar. The inevitable addition of components to accomplish this functionality may lead to security vulnerabilities through various vectors. Hence, we propose a security framework in this study to improve the security of UAS. The proposed framework operates in the ROS (robot operating system) and is designed to focus on several perspectives such as overhead arising from additional security elements and security issues essential for flight missions. The UAS is operated in a non-native and native ROS environment. The performance of the proposed framework in both environments is verified through experiments.YⅠ. INTRODUCTION 1
Ⅱ. BACKGROUND 3
2.1 Unmanned Aerial System (UAS) 3
2.2 Robot Operating System (ROS) 5
2.3 Rosbridge 6
2.4 Safety tool of ROS 6
Ⅲ. VULNEARABILITY DEFINITION OF ROBOT OPERATING SYSTEM 9
3.1 Vulnerability in CPS 9
3.2 UAS data transmission layer model in CPS perspective 10
3.3 Model of ROS-based UAS 11
3.4 Vulnerability of ROS-based UAS 13
Ⅳ. RELATED WORK 15
Ⅴ. PROPOSED METHOD 17
5.1 Registration of a new node 18
5.2 Signature with HMAC 19
5.3 Performance and Conceptual Comparison 21
Ⅵ. TEST 23
6.1 Experiment environment of UAS 23
6.2 Experiment on native ROS attack 25
6.3 Experiment on non-native ROS attack 28
Ⅶ. CONCLUSION 32
REFERENCES 33
SUMMARY (Korean) 35본 논문은 ROS가 적용된 UAS에서의 취약점을 분석하고, 이를 방어할 수 있는 보안 프레임 워크를 제시한다. 최근 여러 상업매체 또는 군에서 동작하는 UAV 는 개별적으로 동작하는 전통적인 임베디드와 달리 컴퓨팅 시스템과 물리시스템이 밀접한 상호작용을 하며 동작한다. 이러한 특성을 갖는 UAV를 운용하는 시스템인 UAS 는 CPS 의 한 범주에 속한다. CPS 는 계산, 네트워킹, 물리적 프로세스가 하나의 피드백 루프로 통합된 시스템을 의미한다. 이 중 네트워킹을 담당하는 데이터 전송 계층은 장소, 상황, 하드웨어, 소프트웨어 등 다양한 통신 네트워크의 접근성을 갖는 CPS 의 특성으로 인해 취약한 계층이다. 이러한 사실은 CPS 의 일부인 UAS 도 같은 취약점을 갖고 있음을 의미한다. 최근 UAV 의 사용은 단순한 비행 미션 수행뿐만 아니라 군집비행, 자율비행 등의 특수한 미션을 수행한다. 해당 미션을 위해서는 컴퓨팅 능력이 있는 하드웨어 및 소프트웨어가 UAS 에 추가 되어야한다. 그 소프트웨어 중 하나로 ROS가 사용되며, 이는 보안적 요소의 부재로 공격자가 로봇 시스템을 망가뜨리는 것을 허용한다. 우리는 ROS 의 보안을 위해 기존에 연구된 내용을 조사하였으며, 해당 방법이 UAS 에 적용 가능한지 여부를 분석하였다. 우리는 시간에 민감한 UAS 에 적용할 수 있는 가벼운 오버헤드를 갖는 보안 프레임워크를 제안한다. 또한 ROS 를 활용할 수 있는 두 가지 접근법인 native ROS 와 non-native ROS 환경에서 실제 실험을 통해 보안 프레임워크의 성능을 검증한다MasterdCollectio
Design and implementation of MLC NAND flash-based DBMS for mobile devices
No full textRecently, Multi-Level Cell (MLC) NAND flash memory is becoming widely used as storage media for mobile devices such as mobile phones, MP3 players, PDAs and digital cameras. MLC NAND flash memory, however, has some restrictions that hard disk or Single-Level Cell (SLC) NAND flash memory do not have. Since most traditional database techniques assume hard disk, they may not provide the best attainable performance on MLC NAND flash memory. In this paper, we design and implement an MLC NAND flash-based DBMS for mobile devices, called AceDB Flashlight, which fully exploits the unique characteristics of MLC NAND flash memory. Our performance evaluations on an MLC NAND flash-based device show that the proposed DBMS significantly outperforms the existing ones. (C) 2009 Elsevier Inc. All rights reserved
12-bit High-Voltage Current-Steering-Assisted R-2R DAC With RCM and Parallel Switch for Satellite Applications
No full textThis work presents radiation hardened by design (RHBD) on a high-voltage (HV) digital-to-analog converter (DAC). A 12-bit HV DAC aiming at satellite applications is configured as a current-steering-assisted R - 2R ladder with common-level control resistors and parallel switches. The DAC structure employs current sources to mitigate the total ionizing dose (TID) sensitivity from switch resistance in a conventional R - 2R ladder. PMOS current sources and polysilicon-based R - 2R networks are utilized to avoid TID-induced leakage. Common-level control resistors are introduced to increase voltage headroom for the current sources. To reduce single-event effect (SEE)-induced bit-flip in control signals, a parallel switches scheme in every unit current source is proposed. An on-chip amplifier facilitates current-to-voltage conversion and output driving. The chip, manufactured in a 0.35- mu m HV CMOS technology, occupies 2.97 mm(2). The TID test was conducted in two phases [up to 116 and 226 krad(Si)] with a Co-60 source. After being exposed to irradiation, the DAC exhibits less than two least significant bit (LSB) of integral nonlinearity (INL) degradation at 116 krad(Si) and then recovers to within 1 and 1.5 LSB from preirradiation at 116 and 226 krad(Si) of the total dose, respectively, after 24 h of room-temperature (RT) annealing. An SEE test with 20 min of 100-MeV proton irradiation shows no evidence of bit upset or fluctuation at the DAC output nodes.
Fine-Grained Multi-Class Object Counting
No full textMany animal species in the wild are at the risk of extinction. To deal with this situation, ecologists have monitored the population changes of endangered species. However, the current wildlife monitoring method is extremely laborious as the animals are counted manually. Automated counting of animals by species can facilitate this work and further renew the ways for ecological studies. However, to the best of our knowledge, few works and publicly available datasets have been proposed on multi-class object counting which is applicable to counting several animal species. In this paper, we propose a fine-grained multi-class object counting dataset, named KRGRUIDAE, which contains endangered red-crowned crane and white-naped crane in the family Gruidae. We also propose a specialized network for multi-class object counting and line segment density maps, and show their effectiveness by comparing results of existing crowd counting methods on the KR-GRUIDAE dataset
Vertically Integrated In-Sensor Processing System Based on Three-Dimensional Reservoir for Artificial Tactile System
No full textNext-generation artificial tactile systems demand seamless integration with neuromorphic architectures to support on-edge computation and high-fidelity sensory signal processing. Despite significant advancements, current research remains predominantly focused on optimizing individual sensor elements, and systems utilizing single neuromorphic components encounter inherent limitations in enhancing overall functionality. Here, we present a vertically integrated in-sensor processing platform, which combines a three-dimensional antiferroelectric field-effect transistor (AFEFET) device with an aluminum nitride (AlN) piezoelectric sensor. This innovative architecture leverages a Zr-rich, leaky antiferroelectric HZO film-a novel material for physical reservoir computing (PRC) devices capable of responding to external stimuli within the microsecond-to-millisecond range. We further demonstrate the 3D AFEFET's adaptability by tuning its discharge current via structural modifications, enabling sophisticated multilayered processing. As an integrated in-sensor processing unit, the 3D AFEFET and AlN sensor array surpass a comparable 2D configuration in both pattern recognition and information density. Our findings showcase a pioneering prototype for future artificial tactile systems, demonstrating the transformative potential of 3D AFEFET PRC devices for advanced neuromorphic applications.
Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer
No full textWe experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal - gate interlayer (G.IL) - ferroelectrics - channel interlayer (Ch.IL) - Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (Q(it)') from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for NAND cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive Q(it) injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-kappa SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing V-th shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation NAND Flash memory technologies.
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