5,822 research outputs found
Visual Object Recognition by 2D-Color Camera and On-Board Information Processing for Minirobots
No full textChinapirom T, Kaulmann T, Witkowski U, Rückert U. Visual Object Recognition by 2D-Color Camera and On-Board Information Processing for Minirobots. In: Proceedings of the FIRA Robot World Congress. Busan, South Korea; 2004
Ressourceneffiziente Realisierung pulscodierter neuronaler Netze
No full textTim KaulmannPaderborn, Univ., Diss., 200
IAF Neuron Implementation for Mixed-Signal PCNN Hardware
No full textKaulmann T, Lütkemeier S, Rückert U. IAF Neuron Implementation for Mixed-Signal PCNN Hardware. In: Sandoval F, ed. Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN). Lecture notes in computer science. Vol 4507. Berlin, Heidelberg: Springer-Verlag; 2007: 447-454.In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation
No full textKaulmann T, Dikmen D, Rückert U. A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. In: Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on. 2007: 302-307.This publication presents a digital framework for build-
ing up pulse coded neural networks with leaky integrate-
and-fire neurons and static synapses as well as dynamic
synapses. The system, including a novel communication in-
frastructure, is mainly focused on ASIC synthesis but also
shows a small footprint on Virtex2(Pro) FPGAs. Its bit-
serial operation has been verified by simulations
Do dolphins benefit from nonlinear mathematics when processing their sonar returns?
No full textAn interview with author Tim Leighton about the paper
Opportunities for linking young surveyors across professional surveying member organisations and FIG
No full textA Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS
No full textLütkemeier S, Kaulmann T, Rückert U. A Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS. In: Semiconductor Conference Dresden. 2009.We have implemented a 32bit ALU operating at voltages from 115mV to 1V on a die area of 0.021mm² in 90nm bulk CMOS. The energy minimum of
0.45pJ/instruction is achieved at a supply voltage of 210mV with the ALUs operating at a clock frequency of 3MHz. A yield of 88.5% can be reported for a supply voltage of 200mV, and 75% for a supply voltage of 120mV
without any body biasing applied. The ALUs have been implemented with an automated design flow and a custom standard cell library, optimized for sub-threshold
operation
Tim Di Muzio on 'Sabotage'
No full textIn a series of essays published in 2013 and 2014 on capitaspower.com, political economist Tim Di Muzio explored the concept of ‘sabotage’ as it applies to capitalist power. I recently rediscovered these essays and was so impressed by them that I have reposted them here as a single piece.
About the author: Tim Di Muzio is a researcher at the University of Wollongong. He is the author of numerous books, including Debt as power, Carbon capitalism, and The 1% and the Rest of us
1996-1997 Tim Gautreaux
No full textTim Gautreaux is the author of three novels and two earlier short story collections. His work has appeared in The New Yorker, The Best American Short Stories, The Atlantic, Harper’s, and GQ. After teaching for thirty years at Southeastern Louisiana University, he now lives, with his wife, in Chattanooga, Tennessee. (Photo credit: Randy Bergeron)https://egrove.olemiss.edu/grisham_res/1023/thumbnail.jp
Universal mini-robot with micro-processor and reconfigurable hardware
No full textKaulmann T, Witkowski U, Chinapirom T, Rückert U. Universal mini-robot with micro-processor and reconfigurable hardware. In: Proc. of FIRA RoboWorld Conference 2006. 2006: 137-142.In this paper, a novel mini-robot is presented that features several new techniques concerning the chassis of the robot integrating electronic components, the usage of information processing principles and the robot's modularity. The core component for the information processing is a PCB integrating processor running Linux and a closely coupled FPGA offering partial reconfiguration of the FPGA resources for optimizing energy efficiency and computing resources
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