221 research outputs found
Challenges and Opportunities in Exascale-Computing Interconnects
No full textKeynote Talk, given by Manolis Katevenis and Nikolaos Chrysos, at the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS 2016), held in conjunction with the HiPEAC 2016 Conference, Prague, Czech Republic, 18 January 2016
Presentation of the ExaNeSt project at the European HPC Summit Week 2016
No full textExaNeSt in 8 slides: Presentation of the ExaNeSt project at the European HPC Summit Week 2016; Prague, Czech Republic, 10 May 2016.www.exanest.e
Telegraphos: High-Speed Communications Architecture for Parallel and Distributed Computer Systems
No full textABSTRACT: Telegraphos is an R&D project in computer communication. It useshardware switches for building high-speed multiprocessor or local area networks; preventive flow control eliminates packet dropping, and dedicated buffers per VCoffer congestion tolerance. The network interfaces have low complexity because they never need to retransmit packets, and because they use a single address space archi-tecture. Message passing is done with the remote write primitive; overhead is minimized because address translation also performs message protection. Other remotememory operations, including eager updates and hardware monitors, provide effective and low-cost support for virtual shared memory. Telegraphos I, our first proto-type, is currently being built
Proceedings of the Third International Conference on High-Performance Embedded Architectures and Compilers
No full textAircraft Marshaling Signals Dataset of FMCW Radar and Event-Based Camera for Sensor Fusion
No full textDataset Introduction
The advent of neural networks capable of learning salient features from variance in the radar data has expanded the breadth of radar applications, often as an alternative sensor or a complementary modality to camera vision. Gesture recognition for command control is the most commonly explored application. Nevertheless, more suitable benchmarking datasets are needed to assess and compare the merits of the different proposed solutions. Furthermore, most current publicly available radar datasets used in gesture recognition provide little diversity, do not provide access to raw ADC data, and are not significantly challenging. To address these shortcomings, we created and made available a new dataset that combines two synchronized modalities: radar and dynamic vision camera of 10 aircraft marshalling signals at several distances and angles, recorded from 13 people. Moreover, we propose a sparse encoding of the time domain (ADC) signals that achieve a dramatic data rate reduction (>76%) while retaining the efficacy of the downstream FFT processing (<2% accuracy loss on recognition tasks). Finally, we demonstrate early sensor fusion results based on compressed radar data encoding in range-Doppler maps with dynamic vision data. This approach achieves higher accuracy than either modality alone.
Dataset Structure
The dataset has a common directory structure which contains additional information about the captures.
dataset_dir///--/ofxRadar8Ghz_yyyy-mm-dd_HH-MM-SS.rad
Identifiers
stage [train, test].
room: [conference_room, foyer, open_space].
person: [0-9]. Note that 0 stands for no person, and 1 for an unlabeled, random person (only present in test).
gesture: ['none', 'emergency_stop', 'move_ahead', 'move_back_v1', 'move_back_v2', 'slow_down' 'start_engines', 'stop_engines', 'straight_ahead', 'turn_left', 'turn_right'].
distance: ['xxx', '100', '150', '200', '250', '300', '350', '400', '450'] (in cm). Note that xxx is used for none gestures when there is no person present in front of the radar (i.e. background samples), or when a person is walking infront of the radar with varying distances but performing no gesture.If you use this dataset, please also cite our accompanying paper:
@inproceedings{mueller2023aircraft, title={Aircraft Marshalling Signals Dataset of Radar and Event-Based Camera for Sensor Fusion}, author={M\"uller, Leon and Sifalakis, Manolis and Eissa, Sherif and Yousefzadeh, Amirreza and Detterer, Paul and Stuijk, Sander, and Corradi, Federico}, journal={IEEE Radar Conference, San Antonio, TX}, volume={}, number={1}, pages={1--15}, year={2023}, publisher={IEE}
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
No full text<p>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.</p>
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