1,720,964 research outputs found

    Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission

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    Differential signaling has become a popular choice for high-speed digital interconnection schemes on printed circuit boards (PCBs), offering superior immunity to crosstalk and external noise. However, conventional differential lines on PCBs still have unsolved problems, such as crosstalk and radiated emission. When more than two differential pairs run in parallel, a line is coupled to the line adjacent to it because all the lines are parallel in a fixed order. Accordingly, the two lines that constitute a differential pair are subject to the differential-mode crosstalk that cannot be canceled out by virtue of the differential signaling. To overcome this, we propose a twisted differential line (TDL) structure on a high-speed multilayer PCB by using a concept similar to a twisted pair in a cable interconnection. It has been successfully demonstrated by measurement and simulation that the TDL is subject to much lower crosstalk and achieves a 13-dB suppression of radiated emission, even when supporting a 3-Gb/s data rate.This work was supported by Center for Electronic Packaging Materials of Korea Science and Engineering Foundation

    Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

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    The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, we have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs

    Modeling and measurement of simultaneous switching noise coupling through signal via transition

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    The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise. is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach
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