1,721,031 research outputs found
Temperature-dependent studies of the electrical properties and the conduction mechanism of HfOx-based RRAM
No full textThe conduction mechanism of HfOx-based RRAM is investigated by analyzing the I-V characteristics of HfOx-based RRAM devices at different temperatures ranging from 350 K down to 40 K. Electrical conduction of RRAM is found to be strongly dependent on the resistance state of the device, electric field, and temperature. At relatively high electric field (E > 3 MV/cm), Poole-Frenkel conduction explains our measured temperature dependence at limited temperature (T > 200 K) and bias ranges while trap-assisted tunneling accounts for the temperature-insensitive conduction regime (T <; 100 K). It is also concluded that the more resistive RRAM device shows weaker dependence on temperature.1
Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training
No full textRecently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.1
ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing
No full textWe demonstrate a nonvolatile Electro-Chemical Random-Access Memory (ECRAM) based on lithium (Li) ion intercalation in tungsten oxide (WO3) for high-speed, low-power neuromorphic computing. Symmetric and linear update on the channel conductance is achieved using gate current pulses, where up to 1000 discrete states with large dynamic range and good retention are demonstrated. MNIST simulation based on the experimental data shows an accuracy of 96%. For the first time, high-speed programming with pulse width down to 5 ns and device operation at scales down to 300×300 nm2 are shown, confirming the technological relevance of ECRAM for neuromorphic array implementation. It is also verified that the conductance change scales linearly with pulse width, amplitude and charge, projecting an ultralow switching energy ~1 fJ for 100×100 nm2 devices.1
Scaling of Al2O3 dielectric for graphene field-effect transistors
No full textWe investigate the scaling of Al2O3 dielectric on graphene by atomic layer deposition (ALD) using ultra-thin, oxidized Ti and Al films as nucleation layers. We show that the nucleation layer significantly impacts the dielectric constant (k) and morphology of the ALD Al2O3, yielding k = 5.5 and k = 12.7 for Al and Ti nucleation layers, respectively. Transmission electron microscopy shows that Al2O3 grown using the Ti interface is partially crystalline, while Al2O3 grown on Al is amorphous. Using a spatially uniform 0.6 nm-thick Ti nucleation layer, we demonstrate graphene field-effect transistors with top dielectric stacks as thin as 2.6 nm.11Nscopu
Low-Frequency Acoustic Phonon Temperature Distribution in Electrically Biased Graphene
No full textOn the basis of scanning thermal microscopy (SThM) measurements in contact and lift modes, the low-frequency acoustic phonon temperature in electrically biased, 6.7-9.7 mu m long graphene channels is found to be in equilibrium with the anharmonic scattering temperature determined from the Raman 2D peak position. With similar to 100 nm scale spatial resolution, the SThM reveals the shifting of local hot spots corresponding to low-carrier concentration regions with the bias and gate voltages in these much shorter samples than those exhibiting similar behaviors in the infrared emission maps.11Nsciescopu
Graphene for CMOS and Beyond CMOS Applications
No full textOwing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm 2 /Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.11Nsciescopu
Reliability Challenges with Materials for Analog Computing
No full textSpecialized hardware for deep learning using analog memory devices has the potential to outperform conventional GPUs by a large margin. At the core of such hardware are arrays of non-volatile-memory (NVM) devices that can perform the simple matrix operations needed for deep learning in parallel and in constant time. Several implementations can be found in the literature that use different materials as memory elements, including phase-change-memory (PCM), resistive-random-access-memory (RRAM), electrochemical-random-access-memory (ECRAM), and ferroelectric devices. While the current focus is to demonstrate functionality, there is an increasing concern about the reliability margins of this emerging technology. In this paper we will briefly describe operation and device requirements, and then focus on possible reliability exposure in terms of variability, stability and drift, retention and durability.1
Metal-oxide based, CMOS-compatible ECRAM for Deep Learning Accelerator
No full textWe demonstrate a CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing. The device demonstrates symmetric and linear conductance update, large on/off ratio and good retention while also withstanding high temperature treatments necessary for BEOL compatibility. Resistive switching in MO-ECRAM is observed with voltage pulses down to 10 ns and scales exponentially with voltage pulse amplitude, enabling parallel array operations without any selector/access devices. For the first time, we experimentally demonstrate fundamental techniques for fully- parallel array operations, stochastic update scheme and zero-shifting technique, and show a successful stochastic gradient descent algorithm demonstration in hardware using a MO- ECRAM array.1
Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity
No full textWe report a capacitor-based cross-point array that can be used to train analog-based Deep Neural Networks (DNNs), fabricated with trench capacitors in 14nm technology. The fundamental DNN functionalities of multiply-accumulate and weight-update are demonstrated. We also demonstrate the best symmetry and linearity ever reported for an analog cross-point array system. For DNNs, the capacitor leakage does not impact learning accuracy even without any refresh cycle, as the weights are continuously updated during training. This makes capacitor an ideal candidate for neural network training. We also discuss the scalability of this array using optimized low-leakage DRAM technology.1
Thickness dependence of carrier mobility in mono- and bi-layer graphene with HfO2 gate dielectric
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