1,721,019 research outputs found
A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX
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A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory
No full textIn this paper, we propose a code inversion encoding technique to improve the read margin of a cross-point phase change memory (PCM). The proposed technique reduces the maximum number of low resistance state cells which significantly reduce read margin by increasing sneak current. Therefore, the proposed scheme can significantly improve the read margin of the cross-point PCM. To verify the improvement of read margin by the proposed technique, we simulated and compared read margins of various arrays with and without the proposed technique. According to the simulation, our technique improves the read margin by 102% or equivalently allows to increase the array size by 91.6% without decreasing for the read margin. The results show that the proposed technique greatly improves the read margin.11Nsciescopu
A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces
No full textWe propose a reflection self-canceling design technique for multidrop memory interfaces. In this technique, lengths of branch lines are designed, so that dominant multiple reflections become self-canceling. As a result, reflective intersymbol interferences (ISIs) can be greatly reduced to increase the bandwidth without utilizing serial resistor insertion, reflection compensation lines (RCLs), or advanced circuits, such as equalization circuits. Using the proposed and the conventional techniques, two eight-drop channels were designed with 50- microstrip lines on FR-4 printed circuit board (PCB) and tested with the pseudo-random binary sequence (PRBS) 31 pattern for comparison. At 10.5 Gb/s, the worst eye height was measured 28.0 mV in the proposed design, while the worst eye diagram of the conventional design was closed. The proposed design achieved the maximum data rate of 12.5 Gb/s and achieved the worst eye height of 10.0 mV. The achieved data rate of 12.5 Gb/s is 95.3% faster than the prior art measured with an eight-drop channel without equalization circuits. © 2011-2012 IEEE.11Nsciescopu
A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS
No full textThis paper presents a transceiver for fast and energy-efficient global on-chip communication, consisting of a nonlinear charge-injecting (CI) 3-tap transmit filter (TX) and a sampling receiver (RX) with transimpedance pre-amplifier (TIA). Recently, pre-emphasis techniques have demonstrated significantly better energy-efficiency than repeater interconnects. To further improve energy-efficiency over pre-emphasis techniques that require analog subtraction, our TX selects a pattern-dependent current to inject into the wire, performing feed-forward equalization (FFE) while mitigating the nonlinearity of the driver. This 3-tap charge-injecting (CI) FFE enables stronger equalization than the capacitively driven TX or edge-detection pre-emphasis, achieving data-rate of 4 Gb/s over a 1 cm on-chip wire. The TIA at RX improves bandwidth, signal amplitude, and reduces bias power, breaking the trade-offs in conventional resistor termination, and mitigates equalized signal degradation due to impedance changes in dynamic current sensing.Massachusetts Institute of Technology. Center for Integrated Circuits and SystemsIntel CorporationSemiconductor Research CorporationNational Semiconductor Corporation. Trusted Foundry Service
A 20 Gb/s/pin 1.18pJ/b 1149um2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS
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A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier
No full textA semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13-mu m CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.X1166sciescopu
Low-Power Small-Area Inverter-Based DSM for MEMS Microphone
No full textA delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3x0025; to 0.06x0025;, reduces the chip area and the power by 32.4x0025; and 24.8x0025;, respectively. The 3(rd) order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).11Nsciescopu
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