1,721,083 research outputs found
RELIABILITY ESTIMATION TECHNIQUES FOR NANOSCALE MOSFETS AND FINFETS CIRCUITS IN THE PRESENCE OF NOISE, VARIABILITY AND AGING
No full textHigh yield, reliability, and increasing number of functions in single Integrated Circuit (IC) have been the continuing demand of the market for IC fabrication. However, the uninterrupted scaling of CMOS and FinFET technologies to nano-scale level leads to fallouts in reliability due to the variability of process parameters and the aging caused by Bias Temperature Instability (BTI). Such issues ultimately become responsible for a weakening of noise immunity in digital circuits which translate in higher logic error probability and higher average power consumption. Various types of failures take part in the degradation of circuit reliability when CMOS and FinFET technologies are scaling to nano meter regime. Failures such as input voltage signal fluctuations in presence of additive noise or crosstalk noise within the circuit topology, variations in process parameters of device itself and different aging mechanisms over the lifetime of circuit, can hugely detoriate the reliability of circuit.
In this thesis work, several novel modeling techniques such as analytical, semi-analytical and approximation, are introduced in order to quantify failure-probability for both combinational and sequential circuits, in the presence of input voltage noise in conjunction with process variations and aging. Furthermore, an analysis on the impact of noise-induced voltage pulses on the static power consumption of nano-CMOS circuits is implemented by using an approximation model scheme. Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This part of research work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and approximation approaches in comparison with SPICE Monte-Carlo verification approach.
Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. The prproposed semi-analytical scheme brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.
Furthermore, the assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis.
Last but not least research devoted to the occurrence of noise pulses on the input signals of idle digital cells has been typically associated to reliability issues, such as transient or permanent logic errors. The wide range of possible noise sources in nano-scale circuits, associated to the variability of process parameters, makes it interesting to explore the impact of random voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised by the noise. This part of the thesis proposes a simple yet effective model to characterize the shift in static energy consumption associated to input voltage pulses in logic cells. The characterization scheme allows a fast calculation of the statistical distribution of the energy shift in multi-cell circuits affected by random noise pulses and considering the impact of device statistical variability. The accuracy and effectiveness of the approach have been tested against SPICE simulation, reaching a four orders of magnitude speedup in run time. All of the above proposed techniques were verified against state of the art SPICE Monte Carlo Simulations and results in over 10E4 faster run time with respect to SPICE evaluation
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
No full textThe assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic
No full textEstimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical approaches in comparison with SPICE Monte-Carlo verification approach
Using safe operation regions to assess the error probability of logic circuits due to process variations
No full textProcess variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of 'safe operation region' to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations. © 2013 IEEE
Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations
No full textSizing and optimization of low power process variation aware standard cells
No full textThe yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations. © 2013 IEEE
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
No full textVoltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >10(4) speedup versus SPICE
Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell
No full textAging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells. © 2015 IEEE
Are Capitalists Green? Firm Ownership and Provincial CO2 emissions in China
No full textIn China, a large private sector has evolved alongside a still sizeable state-owned sector that is subject to government control. Several studies have found that in this mixed economy, the private sector is economically more efficient than the state-owned sector. In this paper, we investigate whether private firms are also more carbon efficient than state-owned firms. Using a macroeconomic panel data model with provincial data from 1992 to 2010, we confirm that private firms emit less carbon dioxide than state-owned firms. Our results imply that future reforms, such as ongoing privatization, introduced to increase the economic efficiency of state-owned companies will also mitigate emissions growth. The policy lesson, not only for China but for developing countries maintaining a large state-owned sector, is that economic efficiency and energy efficiency are conjoined mutual benefits
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