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Oksitlenmiş, Karbonlanmış ve Isılişlemden geçirilmiş gözenekli silisyumdan gün ışığı benzeri beyaz ışıma
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Gözenekli Silisyum Tabanlı Fabry-Perot Yapıların Anodizasyon Şartlarına Ve Yaşlanmaya Bağımlılığı
No full textA new approach to modeling TiO2-x-based memristors using molecular dynamics simulation
No full textThis study aims to investigate the oxygen ion migration in defect rutile titanium dioxide (TiO2-x) in the presence of oxygen and titanium vacancies using a new approach based on molecular dynamic simulation. In this approach, the force field models along with Buckingham and Columbic potentials are used. For this purpose, the simulation is conducted in two different phases. In the first phase, the effect of temperature on the mean square displacements of oxygen ions is examined; besides, the diffusion and ionic conductivity of oxygen are studied in the absence of the electrical field. The results reveal that in the temperature range of 1100-1900K, the oxygen vacancies tend to form clusters. These clusters consist of two oxygen vacancies. In the second phase, the memristor is applied to the model and hysteresis loops are studied in five cycles. The results of the second phase show that the new model correctly predicts the migration behavior of the oxygen ions in the memristor configuration. In conclusion, compared to the models using the Langevin equation method, the proposed model provides information which is closer to reality. Furthermore, the mean square displacements of the oxygen ions versus time are studied in the presence and absence of the electrical field at 300K, and the results indicate greater diffusion in the presence of the electrical field
Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA
No full textPosit arithmetic has attracted a lot of attention as a promising alternative to the IEEE754 floating-point number representation thanks to its advantages such as higher accuracy and dynamic range. However, hardware solutions are not yet mature, as the posit number representation is still in its infancy. Therefore, posit units are more expensive and low performance than IEEE754 floating-point units. In this paper, a parameterizable low-latency posit adder/subtractor architecture is proposed, which contributes to higher performance posit arithmetic units. Normalization, which is quite slow in standard posit adder/subtractor architectures, is accelerated. The leading-one prediction algorithm is used to determine the amount of left shift required for normalization which reduces the delay time by shortening the critical path. Proposed and standard posit adder/subtractor architectures are implemented on Xilinx Zynq 7000 SoC XC7Z020-CLG484–1 chip with exponent bit length 1, 2, 3 and 4 and precision 16, 32, 64 and 128. The proposed adder/subtractor architecture has lower delay time than the standard architecture at 32, 64 and 128 bits. The results show that the proposed posit adder/subtractor has a lower delay time than the standard design by 0.417 ns, 0.398 ns and 2.636 ns for 32, 64 and 128 bits precision, respectively
Design and hardware implementation of bit length adjustable cosine and sine generator with CORDIC algorithm in FPGA Bit Uzunluğu Ayarlanabilir Kosinüs ve Sinüs Üretecinin CORDIC Algoritması Kullanarak Tasarlanması ve FPGA'de Donanımsal Olarak Gerçeklenmesi
No full text© 2020 Turkish Chambers of Electrical Engineers.Today, the need for hardware architectures with fast calculation, high usage area efficiency and accuracy are increasing in digital systems. Therefore, the algorithm used for the hardware to be designed and the number format in which this algorithm operates are quite important. In this study the hardware that calculates the cosine and sinus trigonometric functions commonly used in digital applications is designed in FPGA with Coordinate Rotation Digital Computer (CORDIC) algorithm which combines the three feature mentioned. The designed hardware operates in a two-complement signed integer format and the bit length is adjustable by the user. Thus, a design with the advantages of high speed and usage area efficiency as well as flexibility has been created. Simulation and implementation of the design is done for the Xilinx Artix-7 FPGA model in Vivado software
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