1,228 research outputs found
Quantum K-invariants and Gopakumar--Vafa invariants I. The quintic threefold
No full textWe prove a conjecture of Jockers-Mayr and Garoufalidis-Scheidegger, relating
genus zero quantum -invariants and Gopakumar--Vafa invariants on the quintic
threefold
Quantum K-invariants and Gopakumar-Vafa invariants II. Calabi-Yau threefolds at genus zero
No full textThis is the second part of our ongoing project on the relations between
Gopakumar-Vafa BPS invariants (GV) and quantum K-theory (QK) on the Calabi--Yau
threefolds (CY3). We show that on CY3 a genus zero quantum K-invariant can be
written as a linear combination of a finite number of Gopakumar--Vafa
invariants with coefficients from an explicit ``multiple cover formula''.
Conversely, GV can be determined by QK in a similar manner. The technical heart
is a proof of a remarkable conjecture by Hans Jockers and Peter Mayr.
This result is consistent with the ``virtual Clemens conjecture'' for the
Calabi--Yau threefolds. A heuristic derivation of the relation between QK and
GV via the virtual Clemens conjecture and the multiple cover formula is also
given.Comment: Comments are welcom
Integrality of genus zero Gopakumar-Vafa type invariants of semi-positive varieties
No full textWe give an alternate proof of the integrality conjecture of genus zero
Gopakumar-Vafa type invariants on semi-positive varieties using algebraic
geometry. The main technique is to relate Gopakumar-Vafa type invariants to
quantum -invariants and to utilize the integrality of the latter.Comment: corrected the computation on Proposition 3.
Timing calculations for three level dodecagonal space vector structure from reference phase voltages
No full textA method to obtain pulse width modulation (PWM) timings for a three level dodecagonal (12-sided polygon) voltage space vector structure using only sampled reference values is proposed in this paper. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle to get the timings by using trigonometric calculations. This method requires look-up tables, angle estimation making it difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle within a sector. The proposed method does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. It is also is generic and can be extended to any number of levels with symmetric structures. The algorithm outputs the triangle number and the PWM compare values - that can be used by any carrier based PWM module to obtain space vector PWM like switching sequences. Extensive simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method
A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range
No full textAbstract—Voltage source inverter (VSI)-fed six-phase induction
motor (IM) drives have high 6n ± 1, n = odd-order harmonic
currents. This is because these currents, driven by the correspond-
ing harmonic voltages in the inverter output, are limited only by
the stator leakage impedance, as these harmonics are absent in
the back electromotive force of the motor. To suppress the har-
monic currents, either bulky inductive harmonic filters or complex
pulsewidth modulation (PWM) techniques have to be used. This
paper proposes a harmonic elimination scheme using switched
capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase
inverters fed from capacitors are used on the open-end side of the
motor to suppress 6n ± 1, n = odd-order harmonics. A PWM
scheme that can suppress the harmonics as well as balance the
capacitor voltage is also proposed. The capacitor fed inverters are
switched so that the fundamental voltage is not affected, and the
fundamental power is always drawn from the main inverters. The
proposed scheme is verified with a detailed experimental study.
The effectiveness of the scheme is demonstrated by comparing
the results with those obtained by disabling the capacitor fed
inverters
Cohomological X-independence for Higgs bundles and Gopakumar–Vafa invariants
No full textThe aim of this paper is two-fold. Firstly, we prove Toda’s X-independence conjecture for Gopakumar–Vafa invariants of arbitrary local curves. Secondly, following Davison’s work, we introduce the BPS cohomology for moduli spaces of Higgs bundles of rank r and Euler characteristic X which are not necessary coprime, and show that it does not depend on X. This result extends the Hausel–Thaddeus conjecture on the X-independence of E-polynomials proved by Mellit, Groechenig–Wyss–Ziegler and Yu in two ways: We obtain an isomorphism of mixed Hodge modules on the Hitchin base rather than an equality of E-polynomials, and we do not need the coprime assumption. The proof of these results is based on a description of the moduli stack of one-dimensional coherent sheaves on a local curve as a global critical locus which is obtained in the companion paper by the first author and Naruki Masuda
A 5th and 7th order harmonic suppression scheme for open-end winding asymmetrical six-phase IM drive using capacitor-fed inverter
No full textVoltage source inverter (VSI) fed six-phase induc-
tion motor drives have high
6
n
1
; n
=
odd
order harmonic
currents, due to absence of back emf for these currents. To sup-
press these harmonic currents, either bulky inductive harmonic
filters or complex pulse width modulation (PWM) techniques have
to be used. This paper proposes a simple harmonic elimination
scheme using capacitor fed inverters, for an asymmetrical six-
phase induction motor VSI fed drive. Two three phase inverters
fed from a single capacitor is used on the open-end side of
the motor, to suppress
6
n
1
; n
=
odd
order harmonics. A
PWM scheme that can suppress the harmonics, as well as
balance the capacitor voltage is also proposed. The capacitor
fed inverters are switched so that the fundamental voltage is
not affected. The proposed scheme is verified using MATLAB
Simulink simulation at different speeds. The effectiveness of the
scheme is demonstrated by comparing the results with those
obtained by disabling the capacitor fed inverters. Experimental
results are also provided to validate the functionality of the proposed controlle
Minimization of switched capacitor voltage ripple in a multilevel dodecagonal voltage space vector structure for drives
No full textA multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment
A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-Level Inverter for The Full Modulation Range
No full textA switched DC voltage three level NPC is proposed in this paper to eliminate capacitor balancing problems in conventional three-level Neutral Point Clamped (NPC) inverter. The proposed configuration requires only one DC link with a voltage V-dc/2, where V-dc is the DC link voltage in a onventional NPC inverter. To get rated DC link voltage (V-dc), the voltage source is alternately onnected in parallel to one of the two series capacitors using two switches and two diodes with device voltage rating of V-dc/2. The frequency at which the voltage source is switched is independent and will not affect the operation of NPC inverter. The switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two level inverter in lower modulation range, thereby increases the reliability of the drive system. A space vector based PWM scheme is used to verify this proposed topology
17-level inverter with low component count for open-end induction motor drives
No full textThis study presents a 17-level inverter-based induction motor drive for high-resolution multilevel voltage space-vector (SV) generation. The proposed topology consists of a three-level inverter and a seven-level inverter connected to an open-end winding induction machine. The two inverters are powered by two unequal DC supplies, resulting in a low component count, with just 12 switches and three floating capacitors per phase. The voltage SVs applied by the two inverters are chosen to eliminate circulating power flow and prevent DC bus overcharging. In addition, the switching states of both inverters are chosen in order to keep voltages of all floating capacitors well-controlled. Since the capacitors voltages are controlled using the phase currents, additional pre-charging circuitry is not required. A modulation scheme using level-shifted carriers has also been developed, which can be used with both V/f control and d-q control. The high-voltage inverter has a low effective switching frequency and the low-voltage inverter has a high effective switching frequency, reducing the switching loss. The included results of steady-state and transient testing of an experimental prototype demonstrate that the proposed scheme is suited for industrial drives and traction applications
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